Curtis Monroe wrote:
> I tried to serial boot my TS-7200 today. Its watchdog is set for 1 second. So
> it's impossible to serial boot it without hardware modifications, (or a CPLD
> reprogram).
This is really interesting. I can't imagine why such a short
duration WDT reset would be configured. 2Hz exits the CD4020
which is being further divided by u19 which is generating the
9302 reset. So it is possible a shorter divider chain was
configured.
If u21 is obscured by the particular CF connector on your
board (note it isn't on the board sitting in front of me
nor AFAICT on the board pic displayed on TS's site), you
can follow the connection from u19.58 which is the 2Hz input
to the CPLD. The trace runs partly on the bottom layer
and easily accessible. I'd probably try temporarily
grounding a trace via to attempt disabling the associated
watch dog.
> The EP9301 on my board downloads the serial boot program at 9600bps. It can
> only load 960 Bytes in one second. Not even half of the 2048 Bytes needed to
> load the SerialBlaster Boot loader.
The other possibility is you are hitting the 93xx internal
WDT timeout causing a reset. This must be disabled by
pulling -CS1 low during reset according to the manual, It
also ventures to u19.58 which may be doing so.
However the internal WDT kicked reset looks to be more on the
order of 0.5s (256ms WDT timeout + 256ms reset pulse duration).
Another Cirrus marvel.
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