Hi Mugilan,
> I recently ran into another problem while trying to interface the CMOS
> sensor to the FPGA. The CMOS sensor had 3 main control signals
> (Frame_Valid, Line_Valid and PIXCLK) as an indicator to latch data
> through its 8 bit data bus. Frame_Valid pulses high at active columns,
> Line_Valid pulses high at active rows and fall time of PIXCLK
> indicates stable data to be latched.
Send me the data sheet, and I'll check it out.
> To deal with this, I created a state machine that runs through a
> series of states that check for each control signal consecutively. My
> problem is that my state machine does not work, i.e. the program is
> not in any of the states. I verified this by connecting each state to
> an output pin that pulses high if the machine is within the state. I
> used a logic analyzer to measure these lines and as soon as I finish
> resetting, it starts from state "Initial" and jumps out of the state
> machine loop.
>
> Frankly, I have no clue of what is going on. I have an "ELSE" clause
> at the end of each "IF" statements that specifies it to go to the
> state "Initial" if it fails to meet all the conditions.
>
> I hope you can shed some light on this. Thank you
Whenever you write VHDL code, you should always write a test
bench and simulate it in ModelSim. Altera has a free edition.
If something works correctly in the testbench but not in hardware,
then you either have a timing issue, or an error in your
simulation models. I'm glad to hear you are probing around
with a logic analyzer - thats a good debugging skill.
If you send me the data sheet for the CMOS sensor, I can
probably throw a simple simulation and state machine together.
Send me your state machine code too, and I can provide some
feedback on it for you.
Cheers,
Dave
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