I am trying to collect data from a CMOS sensor at about 1.5MHz. My
plan is to implement a data acquisition state machine within the FPGA
and store one row of data (approximately 1.5kB) each time and send it
to the CPU for computation. All the controls of the row and the time
interval of each data collection will be controlled by the CPU.
To implement this, I think the best way is to store the data into the
FPGA memory block and then send it to the CPU for permanent storage
and computation. I pretty much implemented most of these structures. I
was also planning to use the internal 8 bit high speed bus between the
CPU and FPGA (DATA08-15 through the 74LVC245 bus transceiver to
BD08-15 => shown in TS7300 schematic pg 2) to transfer the data.
Now I am having trouble in finding the corresponding direction
register and the data register for the CPU data lines (DATA08-15).
My questions are:
1) is there a dedicated register to control this data bus? (I know
about the
PC/104 expansion bus but i rather not have additional external lines)
2) if there is, where can I get documentations or sample codes to use
this?
3) if there isn't, can I still go forward with this approach and how
would I proceed?
I really appreciate your help and I hope you can guide me with this
too. I am trying to complete my senior design work (Electrical
Engineering), I have all the hardware part done, just this software
implementation is slowing me down a little. Thank you very much.
Mugilan
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