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Re: [ts-7000] Re: [TS7300] Finding registers or memory address correspon

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Subject: Re: [ts-7000] Re: [TS7300] Finding registers or memory address corresponding to CPU to FPGA bu
From: David Hawkins <>
Date: Sat, 26 Apr 2008 18:45:34 -0700
Hi Mugilan,

> basically the state machine has to check for rise time
> in FRAME_VALID and LINE_VALID and also fall time in
> PIXCLK when Rin is activated (Rin is the signal
> from CPU saying it needs data from CMOS). 
> 
> Once that is achieved I am supposed to latch the incoming
> data from DataCMOS bus to the memory, but for now, I just
> incremented a counter to show that I have saved one
> additional pixel of data. Also after collecting 8 data,
> it supposed to go to state StoreDone and remain
> there until reset (debugging purposes). 

Sorry, these comments are not clear, and neither is
your state-machine, but I'll help you with that.

Please clarify what you are trying to do (relative to
the following comments);

The sensor has 1024 x 1280 x 10-bit pixels.
During image readout, FRAME_VALID asserts high, and
LINE_VALID asserts high in 1280-pixel-clock blocks (Table 10).
During the time FRAME_VALID and LINE_VALID is high, you can
capture the 10-bit data on the falling of the pixel clock.

A 1280-location x 10-bit RAM could capture a single scan,
but all scans would require 1280 x 1024 = 1280k x 10-bits,
or close to 1.6MB of RAM.

 From the sounds of your email, you plan to capture just
one scan at a time, i.e., a 1280-sample line, and by
the looks of your VHDL, you only want 8-bits of the
10-bit sensor output.

Out of interest, how were you planning to get all of the
scan lines? Is there some way to configure the sensor to
just send one line at a time? (I didn't read the whole
data sheet).

Provide feedback on the above, and I can put together some
VHDL pretty quickly, since the interface is not very complex.
Eg, the pixel data can be captured using the falling edge
of the pixel clock. The data can be written to RAM
using an address driven by a counter that is incremented
by the falling edge of the pixel clock. A state machine
would be enabled by the host, perform the capture, and
then assert a ready-acknowledge to the host.

Regards,
Dave


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