Hi Mugilan,
I wrote a testbench, sensor model, and sensor interface
for you.
http://www.ovro.caltech.edu/~dwh/ts7300/cmos_sensor.zip
Unzip that into a folder, eg. c:/vhdl/cmos_sensor
Install Altera's ModelSim-AE and request a VHDL license.
Once you've got it working, start it up and;
cd c:/vhdl/cmos_sensor
source scripts/sim.tcl
sim_sensor
On the right-top will be a source window. Close that.
Under that window will be the waveforms window.
The testbench output the following waveforms:
http://www.ovro.caltech.edu/~dwh/ts7300/sensor_tb.pdf
http://www.ovro.caltech.edu/~dwh/ts7300/sensor_tb_zoom.pdf
The sensor model I created generates the frame_valid
and line_valid signals after receiving a trigger pulse.
The line_valid signal is asserted for 10 data phases.
The capture FSM is enabled by the capture_enable signal
from the host, and when data is captured, it asserts
capture_done.
Note that you should read the code very carefully.
Signals from the hosts clock domain need to be
synchronized when sent to the sensor clock domain,
and vice versa.
I didn't add the RAM component. The RAM would be dual
ported, with the host side clocked by the host clock,
and the sensor side clocked by the sensor clock.
This should get you started.
Cheers,
Dave
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