--- In David Hawkins <> wrote:
>
> Hi Mugilan,
>
> > basically the state machine has to check for rise time
> > in FRAME_VALID and LINE_VALID and also fall time in
> > PIXCLK when Rin is activated (Rin is the signal
> > from CPU saying it needs data from CMOS).
> >
> > Once that is achieved I am supposed to latch the incoming
> > data from DataCMOS bus to the memory, but for now, I just
> > incremented a counter to show that I have saved one
> > additional pixel of data. Also after collecting 8 data,
> > it supposed to go to state StoreDone and remain
> > there until reset (debugging purposes).
>
> Sorry, these comments are not clear, and neither is
> your state-machine, but I'll help you with that.
>
> Please clarify what you are trying to do (relative to
> the following comments);
>
> The sensor has 1024 x 1280 x 10-bit pixels.
> During image readout, FRAME_VALID asserts high, and
> LINE_VALID asserts high in 1280-pixel-clock blocks (Table 10).
> During the time FRAME_VALID and LINE_VALID is high, you can
> capture the 10-bit data on the falling of the pixel clock.
Thats true. At rise time of FRAME_VALID and a consequent rise time of
LINE_VALID will prove that the sensor is reading from the very first
row (also very first pixel). Following this, I can capture pixel data
from the beginning.
> A 1280-location x 10-bit RAM could capture a single scan,
> but all scans would require 1280 x 1024 = 1280k x 10-bits,
> or close to 1.6MB of RAM.
>
> From the sounds of your email, you plan to capture just
> one scan at a time, i.e., a 1280-sample line, and by
> the looks of your VHDL, you only want 8-bits of the
> 10-bit sensor output.
At the falling edge of PIXCLK, I plan to capture the 8 MSBs of the
10-bit pixel data. Yes, I also plan to capture one row of data at one
time.
> Out of interest, how were you planning to get all of the
> scan lines? Is there some way to configure the sensor to
> just send one line at a time? (I didn't read the whole
> data sheet).
I don't think you can do that. You can mess around with horizontal and
vertical blanking but thats just going to be used to specify the
active sensor area, not capture one specific row. I only need to
capture a few specific rows of th CMOS sensor. If I can capture one
row at a time, I can just put a counter on rise time of LINE_VALID to
capture specific row later on.
> Provide feedback on the above, and I can put together some
> VHDL pretty quickly, since the interface is not very complex.
> Eg, the pixel data can be captured using the falling edge
> of the pixel clock. The data can be written to RAM
> using an address driven by a counter that is incremented
> by the falling edge of the pixel clock. A state machine
> would be enabled by the host, perform the capture, and
> then assert a ready-acknowledge to the host.
Yep, address driven by a counter is what I wanted to do too. You got
exactly what I wanted to do :
1) Capture one row of data when instructed.
2) Save it into FPGA Memory
3) Send acknowledge to host (CPU)
Later when host asks to send data from FPGA Memory, set a counter that
runs through the memory addresss one by one and passes it to host.
> Regards,
> Dave
>
Hope that clarifies things further, thank you Dave.
Mugilan
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