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Re: [ts-7000] Re: [TS7300] Finding registers or memory address correspon

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Subject: Re: [ts-7000] Re: [TS7300] Finding registers or memory address corresponding to CPU to FPGA bu
From: David Hawkins <>
Date: Wed, 23 Apr 2008 13:24:17 -0700
Hi Mugilan,

> I understand what you are trying to say. You are concerned with the
> speed of transfer between the FPGA and CPU. Let me clarify, I plan to
> grab one set of data from the CMOS sensor and save it in the FPGA
> block RAM at first. Then, I want to let the CPU take all the time it
> needs to successfully save these data set into its memory before
> instructing the FPGA to grab a new data set. i.e. only the FPGA has to
> comply with the 1ms time constraint. 

Ok, no problem then.

> For this, I have implemented a state machine that saves the data from
> the CMOS sensor into the FPGA's Block RAM. This state machine also
> must the capability to transfer the data to CPU once instructed.

Thats not quite right (or perhaps your description is not clear).
Let me tell you how I would code the interface:

  ------     --------------------------------------------------------
| CPU  |<->| Bus target interface<->Dual port ram<->Sensor interface|
  ------     --------------------------------------------------------

To implement this interface, you would

1) Implement the CPU target interface to RAM.

    Basically you want to capture the address, and write-data,
    or capture the address, assert a wait-state signal until
    read data is ready.

2) Once you can interface to RAM, you can interface to anything.

    In your case, you want to interface the second port of the
    dual port RAM to the sensor.

    In this way, you can use the 16-bit interface from the CPU
    to transfer data captured from the 8-bit interface of the
    sensor. Even if the RAM does not support 8-bit to 16-bit
    conversions, its pretty simple to capture two sensor samples
    and then write them to RAM, or read two 8-bit samples from
    RAM to deliver to the processor as a 16-bit word.

> For this, I created a state that latches the data (8 bits) from
> FPGA's Block RAM to the DB08-15 bus when a physical input line
> from the CPU is pulsed high. 

Its generally not that simple. What you need to ensure is that
the memory map of the CPU is configured to assert the correct
read/write control signals to the FPGA. The opencores.org
FPGA image will have that interface already.

> Now, I need the capability for the CPU to store this 8-bit data and
> signal the FPGA to latch another 8-bit data using a second physical
> input line. I have done the physical line instruction part by
> connecting some of the DIO1 and DIO2 pins. I figured that if there is
> a data and direction register corresponding to the DATA08-15 bus of
> the CPU, I can synchronize the data transfer and it would complete my
> project. I was wondering if you can help me with this issue.

Sure I can help, I might even fire up my TS-7300 and implement
the CPU interface, but I don't want to spoil your fun, or
do your homework for you :)

> I don't know if the FPGA has the capability to directly store data
> into the CPU but I am sure I cannot save the data into the CPU's SDRAM
> directly.  

The FPGA can not be a 'bus master' of the bus between the CPU
and the FPGA. You have to use the CPU to initiate the read/write
access. The SDRAM is on the FPGA pins, so its controlled by the
FPGA.

> And also if you can pinpoint an example file in opencores.org, it
> would be really helpful because I tried looking at that earlier but
> all I am finding is VHDL codes and no traces of pinpointing register
> addresses. 
> 
> Thanks a lot for your help.

The web page I originally looked at, but didn't get time to investigate
further was;

http://www.opencores.org/projects.cgi/web/ts7300_opencore/overview

which has Verilog code to interface the CPU to the FPGA.

I prefer VHDL, so was going to write my own interface. But I
haven't had a chance.

Take a look at this code, and explain it to me (so that I know you've
looked at it), and if you're totally confused, I'll give you some
pointers.

When is your project due?

Cheers,
Dave



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