Hi Dave,
Thanks alot for your help. I read your code carefully and I think I
understand what is going on. The simulation using MODELSIM is great, a
much better way than using the inherit Quartus II simulator.
Here's what I understand of your code, correct me if I'm wrong.
I can see you have created a FSM that checks for Frame_Valid and
Line_Valid to be high. If that is the case, then it increments a
counter that corresponds to a incrementation of memory address. Also,
there is a "high" in write enable signal to make sure the data is
latched to memory. When the Line_Valid goes low, then it goes to state
S_Done and stays there until capture_enable goes low.
One thing I noticed is that you assigned pixclk to the FSM's clock. I
used a clock that is at least 5 times faster than pixclk. My reasoning
for that is because faster means no errors in missing a pixclk edge (I
used pixclk as an input and checked for its fall time). Also I loading
the code with the TS-7300 board and my CMOS sensor. Here's a little
bit of problem.
When the capture_enable goes high and stays high, the FSM supposed to
stay in S_Done state after the first instance of Line_Valid goes low.
My problem is that it stays there for some while and then later it
jumps back to S_Idle and runs back through the state machine again.
Now, I tested this using a logic analyzer and alternatively an
oscilloscope. both produced the same results. I did notice that it
stays in the FSM all the while, no running outside of the loop. I need
to point out that I used a manual input (vcc signal on breadboard
using wires) for the rstN and the capture_enable signal. I realize
that I need to sync the inputs with the sensor's clock when I connect
the host (CPU) to the sensor. But as far as I can see from this manual
input (I connected it to an oscilloscope and logic analyzer) it does
not go low at all (no disturbance). How would you explain this? To be
honest, I still do not fully understand why we need to sync the inputs
to the sensor's clock :).
I really appreciate you help in this. And seeing your codes, I wished
they actually thought me how to organize it as well as you did in my
classes before (taking one lab class to code VHDL is barely enough to
cover everything). I mean, I did not know how to link 2-3 VHDL files
with different entities and connect them in a top-level VHDL file
using "component" and "port map" commands. I will implement the memory
blocks in such way, I think all I need is a 1024 words with each 8-bit
long. And I think I should use not_pixclk for the clock input of the
memory. Can I just use a clock that is like 5-10 times faster than
pixclk instead??
Also, I did notice that you just checked for highs in Frame_Valid and
Line_Valid and not their rise time. This way, I don't think it will
start scanning from the first row, i.e. Frame_Valid and Line_Valid can
already be high at the time where you start scanning meaning that it
could be scanning the pixels from the middle part of the CMOS sensor
and not the very top.
Thanks again for your help. Have a great day.
Mugilan
--- In David Hawkins <> wrote:
>
> Hi Mugilan,
>
> I wrote a testbench, sensor model, and sensor interface
> for you.
>
> http://www.ovro.caltech.edu/~dwh/ts7300/cmos_sensor.zip
>
> Unzip that into a folder, eg. c:/vhdl/cmos_sensor
>
> Install Altera's ModelSim-AE and request a VHDL license.
> Once you've got it working, start it up and;
>
> cd c:/vhdl/cmos_sensor
> source scripts/sim.tcl
> sim_sensor
>
> On the right-top will be a source window. Close that.
> Under that window will be the waveforms window.
>
> The testbench output the following waveforms:
>
> http://www.ovro.caltech.edu/~dwh/ts7300/sensor_tb.pdf
> http://www.ovro.caltech.edu/~dwh/ts7300/sensor_tb_zoom.pdf
>
> The sensor model I created generates the frame_valid
> and line_valid signals after receiving a trigger pulse.
> The line_valid signal is asserted for 10 data phases.
>
> The capture FSM is enabled by the capture_enable signal
> from the host, and when data is captured, it asserts
> capture_done.
>
> Note that you should read the code very carefully.
> Signals from the hosts clock domain need to be
> synchronized when sent to the sensor clock domain,
> and vice versa.
>
> I didn't add the RAM component. The RAM would be dual
> ported, with the host side clocked by the host clock,
> and the sensor side clocked by the sensor clock.
>
> This should get you started.
>
> Cheers,
> Dave
>
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