Hi Zhaomin,
> Thank you very much for your excellent advice!
> As you described, there're two devices (FPGA, ARM processor) that
> access the SDRAM. From my understanding, FPGA and ARM processor use
> different SDRAM (8MB for FPGA, 32MB for ARM cpu) and some memory
> space are mapped together. Is my understanding right?
Yes. The ARM CPU SDRAM controller is used to control the SDRAM
that the ARM core considers 'memory' (for programs etc).
The 8MB of SDRAM that is controlled by the FPGA pins is yours
to play with, its 'device memory'. The TS VGA core will use it
as VGA memory, however, I'm sure you can 'borrow' some of it
and tell the VGA not to use it.
I don't believe that the TS VGA core could be used in a custom
design without paying for a copy of the core. You're probably
going to want to use something from the opencores web site.
I haven't used any opencores code, so I can't help in that
respect.
> Does the wishbone bus act as the arbiter? Or do I need to design
> the arbiter within FPGA? How does the arbiter interact with the ARM
> cpu?
I'm not sure what arbiter logic the wishbone interface supports.
Generally you just add it as an extra layer between devices,
eg. if I had an SDRAM controller with the ports sel, rdwrN,
wait, wrdata, and rddata, and I had two devices to access the
SDRAM, then I would create a component with three ports,
eg,
-- Master device #A
a_selN
a_rd_wrN
a_wait
a_wrdata
a_rddata
-- Master device #B
b_selN
b_rd_wrN
b_wait
b_wrdata
b_rddata
-- SDRAM controls
selN
rd_wrN
wait
wrdata
rddata
The a_selN and b_selN controls go to the arbiter, and the
first one to select the SDRAM wins. Eg. if a_selN is asserted,
then A gets to control the SDRAM until its done. If b_selN
asserts, then b_wait is left asserted until A is done.
The component contains a multiplexer for a_wrdata and
b_wrdata to the SDRAM wrdata port. rddata from the SDRAM
just goes to a_rddata and b_rddata directly. The A and B
controls are possibly multiplexed onto the SDRAM controls,
or they are just constructed as part of the arbiter FSM.
You may also end up registering the control signals, creating
an extra clock cycle of delay, but increasing the fmax of
the design.
Look in the opencores site for arbiters, or Google it, they're
explained in lots of places.
Cheers
Dave
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