Thank you very much for your quick response!
Now I agree with you that I need to write a FPGA code to FIFO the
byte data from XDIO to a block of memory in SDRAM. I plan to revise
the ts7300-opencore to achieve this.
Since most memory in FPGA is reserved for video-core or sd-core, what
I want to use is the RAM reserved for ethernet (because I don't need
the ethernet in the final product). The manual saids that Ethernet
packet ram from 0x7210_0000 - 0x7210_ffff (32-bit, 8Kbyte).
Is there a simple code that I fifo the pixel data to the 8KB ram
synchronously (1 pixel per 41.7ns)? that is
pixel 1 (DIO0 to DIO7)-> 0x7210_0000
wait 41.7ns
pixel 2 (DIO0 to DIO7) -> 0x7210_0001
wait 41.7ns
pixel 3 (DIO0 to DIO7) -> 0x7210_0002
wait 41.7ns
pixel 4 (DIO0 to DIO7) -> 0x7210_0003...
Thanks,
Zhaomin
--- In David Hawkins <> wrote:
>
> You'd need to explain your CMOS interface.
>
> If the sensor uses a read-control signal, and data
> bits, and your controlling those, then all you'd have
> to do is slow the sensor enough that you could read
> 640 times before the next frame.
>
> However, if the sensor just writes out 640-samples at
> a fixed clock rate, you'd be better writing some FPGA
> code.
>
> I haven't used the XDIO interfaces other than to test
> toggle rates. Its possible there is a mode that you
> can use them in, but I couldn't comment on it.
>
> Given that you can slow the sensor down, the FPGA code would
> be as simple as a FIFO. The sensor would write synchronously
> to the FIFO, while the Linux code would read from it
> (asynchronously). So long as the worst-case latency of
> Linux is absorbed by the FIFO, you shouldn't lose any
> data. If you're more adventurous, then have the FPGA
> write to SDRAM, and then read from SDRAM.
>
> I hope that gives you some ideas,
> Dave
>
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