[ts-7000] TS-7300 FPGA interface VHDL+simulation

[David Hawkins <>]

Hi,

I know that Jesse Off has published an opencores project at

http://www.opencores.org/projects.cgi/web/ts7300_opencore/

and that the interface is written in Verilog, and that
others have posted wrappers to VHDL. However, ...

I would like to create a completely VHDL version of the
project, and add a bus functional model (BFM) that can be
used to generate transactions from within ModelSim. That
way people can simulate their designs from the comfort
of ModelSim prior to downloading to the board.

I'll post the project back to opencores.

The project needs to be entirely written in either Verilog
or VHDL, as the free version of the Altera Edition of
ModelSim (ModelSim-AE) forces you to select support for
either VHDL or Verilog. I happen to prefer VHDL.

Jesse's opencore's project doesn't contain a simulation
of read or write transactions, so it makes it a bit
tricky to understand the mapping from the original EP9302
external memory interface into the TS-7300 interface.
Hopefully Jesse reads this and will respond.

I took a few scope captures, and looked at the bus setup
of the EP9302, and would like a little more explanation,
if only to 'get inside the head' of the guys who originally
designed the interface.

So here goes ...

1. The EP9302 external memory bus can be configured to
    use synchronous memory or asynchronous memory.

    Any reason why you didn't interface the FPGA as a
    synchronous device? It looks like the EP9302 synchronous
    controller can be setup to interface to SyncFlash and
    SyncROM. It would imagine the FPGA could emulate one
    of these synchronous devices. In that case burst
    transactions would be faster than asynchronous mode.

    Please don't take offence ... its just meant as a
    question :)

2. The EP9302 asynchronous SRAM interface uses the following
    controls;

    From p6 of the EP9302 data sheet;

    CS#7 (maps to 0x70000000, p45 of the EP9301 User Manual)
    AD[25:0]
    DA[15:0]
    DQM#[1:0]
    WR#
    RD#
    WAIT#

    And the data sheet shows all the usual timing waveforms
    with respect to programmable wait-states (WST1 and WST2)
    etc. It wouldn't take too much work to create a
    bus functional model of a read() and write() function
    for use in Modelsim to generate these waveforms.
    However ...

    The FPGA interface has the following signals;

    FL_D[7:0]
    BD[15:8]
    ISA_ADD[15:11, 1]
    ADD[20:17]
    START_CYCLE#
    BD_OE#
    ISA_WAIT#

    A little more detail on the following would help my
    understanding ...

    * START_CYCLE# pulses low for what appears to be the
      length of the transaction. Does this have the same
      timing as CS#7, or is the MAX II CPLD adjusting it?

    * BD_OE#, is this the WR_RD# control, or just a bus
      control?

      Looking at the Verilog, it looks like a WE signal
      is getting extracted from FL_D[7].

      How do you distinguish transaction types?

    * The 16-bit data bus is BD[15:8] & FL_D[7:0], but it
      looks like some of the address bits get muxed onto
      the FL_D[7:0]. Actually from the Verilog it looks
      like address bits get muxed in reverse order.

      Whats the timing on these signals? Eg. valid on the
      falling edge of start_cycle#?

I tend to prefer using finite-state-machines to describe
bus interface logic. It simulates nicely (in that you can see
the enumerations of the states as the transaction progresses),
and the FSM-style generally forces all control signal logic
values to be covered (no weird lock-ups).

Here's what I envision for the VHDL interface ...

  * START_CYCLE# asserts low
  * the falling edge of START_CYCLE# is used to latch
    the address and data bus signals.
  * the falling edge of START_CYCLE# is used to generate
    a synchronized pulse in the 75MHz domain of the FPGA.
  * the 75MHz logic captures the address and data,
    and the transaction type
  * ... transaction proceeds ...

I just need to fill in more of the details :)

At a minimum, if Jesse generated a Quartus simulation file for
read 8-bit, 16-bit, 32-bit, and write 8-bit, 16-bit, 32-bit,
for his current interface, I think I could figure out the
conversion into VHDL.

Thanks!
Cheers,
Dave.








 
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