Hi Zhaomin,
> Now I agree with you that I need to write a FPGA code to FIFO the
> byte data from XDIO to a block of memory in SDRAM. I plan to revise
> the ts7300-opencore to achieve this.
ok.
> Since most memory in FPGA is reserved for video-core or sd-core, what
> I want to use is the RAM reserved for ethernet (because I don't need
> the ethernet in the final product). The manual saids that Ethernet
> packet ram from 0x7210_0000 - 0x7210_ffff (32-bit, 8Kbyte).
If you are writing the FPGA code, you can make the FPGA memory
map anything you like. Just eliminate the ethernet and VGA.
In fact, the opencore project only has ethernet. The SDRAM
is free to use. However, you don't even need that to implement
a FIFO interface.
> Is there a simple code that I fifo the pixel data to the 8KB ram
> synchronously (1 pixel per 41.7ns)? that is
> pixel 1 (DIO0 to DIO7)-> 0x7210_0000
> wait 41.7ns
> pixel 2 (DIO0 to DIO7) -> 0x7210_0001
> wait 41.7ns
> pixel 3 (DIO0 to DIO7) -> 0x7210_0002
> wait 41.7ns
> pixel 4 (DIO0 to DIO7) -> 0x7210_0003...
Altera's Quartus tool will let you instantiate a dual-ported
FIFO, with dual-clocks. You use the CMOS sensor clock to clock
data into one side of the FIFO, and you use a wishbone interface
to the otherside of the FIFO to read it back using the ARM
processor.
If you've never done any sort of hardware/Verilog/VHDL before
this might be a bit confusing. If you could provide info
on the CMOS sensor, I might be able to help.
Cheers,
Dave
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