Hi, Dave,
Thank you very much for your excellent advice!
As you described, there're two devices (FPGA, ARM processor) that
access the SDRAM. From my understanding, FPGA and ARM processor use
different SDRAM (8MB for FPGA, 32MB for ARM cpu) and some memory
space are mapped together. Is my understanding right?
Does the wishbone bus act as the arbiter? Or do I need to design
the arbiter within FPGA? How does the arbiter interact with the ARM
cpu?
Thanks,
Zhaomin
2007/5/28
--- In David Hawkins <> wrote:
> - since there are two devices that access the SDRAM,
> you'll need an arbiter and some logic to select who
> is in control of the SDRAM.
> Good luck!
> Dave
>
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