Hi Zhaomin,
The data sheet shows that the sensor has two interfaces;
the serial control interface, and the sensor interface.
The serial control interface can be bit-banged, since
you send it the clock, and the data. However, if you're
going to write FPGA code, it would be fairly simple to
convert the serial interface into a set of parallel
FPGA registers and have the FPGA perform the serial
transaction.
The sensor interface is indeed synchronous. The first
thing I would do is write a Modelsim simulation of the
sensor output interface, i.e., generate VSYNC, HSYNC,
and data frames. Then I'd write the HDL to capture the
data from the simulator.
So how do you plan to use the sensor; like a single-shot
camera, or a continuous frame device? Lets start with
single-shot mode. So you enable the camera, and it
starts generating 10-bit output data. Your FPGA code
will be clocked by PCLK, and it looks like HREF high
indicates when data can be written to the FIFO.
So first thing I'd try is creating a FIFO, hooking the
clock to PCLK, and the input data to the 10-bit sensor
output, and then use HREF as the FIFO write-request
control.
Now, how fast do you need to read the FIFO ....
VGA mode; 640 pixels per line x 480 lines, so thats
307200-samples (300k-samples). The samples are being
written at 24MHz, so all 300k samples are written in
12.8ms. If you're only writing 8-bits of sensor data,
then the write rate is 24MB/s.
The Cyclone 2C8 has 36 M4K blocks. Lets say you use 32
to create an 8-bit x 16k FIFO. Clearly its not big
enough to store all the data.
In the XDIO toggle I/O test I wrote, you can *write* to
the FPGA at 145ns per write. I didn't check reads, but
lets assume its the same. So if you perform one 8-bit FIFO
read every 145ns, the read rate is 6.9MB/s, i.e., since
this is less than the write-rate your FIFO will overflow.
The FIFO could be used with a write width of 8-bits and
a read width of 16-bits, so your read bandwidth would
double to 13.8MB/s. This is still not fast enough to
read the sensor data before it overflows the FIFO.
You could try to clock the sensor at 12MHz, and things
*might* work, but the sensor bandwidth would be 12MB/s,
while the CPU interface bandwidth would be 13.8MB/s,
so things would still be pretty tight. (No allowance
for OS overhead).
So my recommendation would be to create a design where;
- the sensor writes to a FIFO using PCLK at
whatever frequency you want.
- have a state machine read from the FIFO and
write to the SDRAM. This state machine, the
read-side of the FIFO, and the SDRAM controller,
would be clocked using the FPGA 75MHz clock.
- have the ARM processor read data from the SDRAM
- since there are two devices that access the SDRAM,
you'll need an arbiter and some logic to select who
is in control of the SDRAM.
- a state machine and a set of control registers;
enable the sensor control, frame complete status, etc.
If you've never programmed FPGAs or used VHDL/Verilog
before then this will be fairly challenging.
Good luck!
Dave
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