--- In Curtis Monroe <> wrote:
>
> PCB Design Impressions:
>
> Nice Work!!!
ty
>
> I know this isn't TS-72XX specific, but I think users of this
forum may find
> comments about your board interesting so I'll post my contribution
here:
>
> ( the EP93XX forum is a better location for this discussion:
> http://arm.cirrus.com/forum/index.php )
>
> ( EP9302 development board schematics, etc, can be found here:
> http://arm.cirrus.com/files/ )
thanks
sorry i forgot to ask for people to email queries / bug reports
direct to avoid flooding this list
its should be written on the schematics as contact email
but forgot to mention it in the first posting here
>
> 1) 1K Pull-up/down resistors on the EP9302 seem a little strong.
I've heard
1/. none of the resistor values have been set yet some have been set
to app note values but are still going to be recalculated
see todo note on last sheet and first sheet
also applies to caps but correct footprints where set for both on
the pcb
> 2.2K Ohm recommended. A 1K resistor will pass 3.3mA for the EP9302
to
> sink/source. Although CS pins can sink up to 4mA its a waste or
power for
> designs that require energy efficiency. I've also heard that
standard 4.7KOhm
> can have insufficient rise-time. The EP9302 latches the state of
these pins
> on reset, so it needs these pins to stabilize quickly at start-up
(unless the
> controller is held in reset by external circuitry).
>
> 2) CS3n (Future use latch), CS2n (Watchdog duration latch) should
be pulled
> up, and CS1n (Watchdog reset timer latch) should be pulled down.
2/. missed that in the data sheet will check it
>
> 3) RTCXTALI needs a clean square 32KHz clock, or the EP9302 will
not boot.
> There is an ERRATA concerning this. TS uses a CPLD, and external
binary
> counter chip to create this waveform.
3/. noted and added to todo list
>
> 4) 100pF seems very high for the 14.7MHz crystal, 20pF is more
likely. (but I
> see none of you cap values are set)
see note 1/.
>
> 5) The 14.7MHz crystal should have a high value bias resistor
(1MOhm) across
> its leds. (I don't know if this is necessary, but its in the
EP9302
> development board schematics). I can't find documentation on this.
>
5/. will check this
> 6) All you bypass capacitors are too small to boot the initial
board. You can
> use the examples from the EP9302 development board to get started.
look here:
cap values also not set see note 1/.
>
http://arm.cirrus.com/files/index.php?path=schematics%2Fedb9302%2F8_Schematics/
>
> 7) Consider a .1uF cap across the GND and 3V3 pins of the JTAG
header.
>
> 8) FB1 and FB2 are resistors
8/.same footprint , diferent schematic symbol ,noted to change it
>
> 9) The resistors values to adjust the output voltage for the LDO
Regulators
> does not seen to be set.
>
see note 1/.
> 10) You might want a Ferrite Bead on the input power header to
reduce high
> freqency noise that may be passed through the LDO regulators
>
10/. added to todo :)
was hoppeing someone would spot this
> 11) All capacitor values on LDO Regulators need adjusting
>
> 12) The Ethernet Phy is named KS8271CL it should be KS8721CL
(2<=>7 reversed,
> typo)
12/. missed this typo
>
> 13) There are no Magnetics for the RJ45? is this a MagJack?
>
13/. yes its a MagJack , ty though think i did not finish its
wireing fully
> 14) I think your EEPROM may only be 1KByte (8Kbit) you'd want
2KByte (16Kbit)
> for the Boot EEPROM. For $1 more you could have a 8KByte boot ROM,
this may
> be enough to let you show the boot process on the screen, without
accessing
> flash.
14/. noted , but bigger device is avalable in same pacakage and
pinout but not updated the device part number
>
> 15) The LDO Regulators and their corresponding diodes may
dissipate a lot of
> heat. I'm not sure what the mAmp requirements are for this board,
but with
> the VGA, FPGA, Ethernet, and all those memory chips it must be
significant
> (at least by California standards).
>
is acctualy hopping that its not too bad , but will do a thermal
calculation and power disipation
> 16) There is a Power-up-Lock errata and work around for the
EP9302. Effort has
> been made to correct the problem but it still exists in the
lastest silicon
> revision. A simple simple fix for this is an external watchdog
timer that
> gets set at reset/power-up and cleared by the boot code. This
could be
> implemented in the CPLD
>
16/. yes known about , the cpld handles the power on reset and
watchdog and that bug is partaly solved by the cpu beeing in reset
at power on while the fpga configuration is loaded
thanks for the feedback , desining it without any up to now other
than RFC's, so its good to get reports of things i missed or did not
spot
> All for now...
>
> -Curtis.
>
>
> On May 4, 2006 11:44 pm, pickanameanditstakensoihavethis wrote:
> > hi
> > well now the first step is done
> > the initial schematics are now complete
> >
> > http://www.whipy.demon.co.uk/geep-sch.pdf
> >
> > and the coresponding pcb artwork
> >
> > http://www.whipy.demon.co.uk/geep.pdf
> >
> > we now would like some to look it over and let us know if there
are
> > any potential problems before we commit to having the prototype
pcbs
> > made
> >
> > the geep is a open source GNU GPL licenced unit
> >
> > it offers
> > ep9302 200Mhz arm cpu
> > up to 256MB of sdram
> > 512MB of on board flash
> > T10/100 ethernet
> > 2 * usb
> > rs232
> > ps/2
> > ac97 audio codec
> > ide
> > compact flash
> > 2 * 100khz to 25Mhz DSS frequency genorators
> > a spartan 3 xc3s400 fpga (75% avalable for user ip)
> > 64MB ddr video ram
> > dvi-i video (both digital and analog)
> > composite video output
> > a 32 dio fpga port / expansion bus ( allowing for 50Mhz +
signal
> > clocking )
> > a lower speed dio and analog expansion port
> >
> > on a 160mm * 100mm 4 layer pcb
> >
> > if verification of the design goes ok then the prototypes
should be
> > under construction in the next 3 months , and allowing another 2
to
> > 3 months for the software port and ip core writing before the
design
> > is totaly finalised
> >
> > anyone interested in getting involved in the development ether
email
> > me at the email on the schematics , or in irc chat on
freenode.net
> > channel #openhardware
> >
> > (sorry that this is slightly off topic)
> >
> > Dave (achiestdragon)
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > Yahoo! Groups Links
> >
> >
> >
> >
> >
> >
> >
> >
>
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