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Re: [ts-7000] new GNU openhardware ep9302 based SBC

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Subject: Re: [ts-7000] new GNU openhardware ep9302 based SBC
From: Christopher Friedt <>
Date: Mon, 08 May 2006 10:52:05 +0000

I could volounteer to port some of this hardware design over to gEDA
tools if you like.

I'd also be very interested in using this board, regardless of which
license was applied to it. However, it would be nice to be able to use
it under a more flexible license for commercial purposes.

Might I suggest that you consider a Xilinx FPGA instead? I have not used
Altera's IDE in quite some time, but ... just checking ... yup, still
requires the purchase of a license. Xilinx's linux suite is all free to
download if you create a username on their site.

~/Chris

pickanameanditstakensoihavethis wrote:
> hi          
> well now the first step is done          
> the initial schematics are now complete         
>          
> http://www.whipy.demon.co.uk/geep-sch.pdf        
>         
> and the coresponding pcb artwork         
>         
> http://www.whipy.demon.co.uk/geep.pdf        
>         
> we now would like some to look it over and let us know if there are         
> any potential problems before we commit to having the prototype pcbs  
> made          
>         
> the geep is a open source  GNU GPL licenced  unit         
>         
> it offers         
>  ep9302  200Mhz arm cpu        
>  up to 256MB of sdram      
>  512MB of on board flash       
>  T10/100 ethernet    
>  2 * usb    
>  rs232    
>  ps/2   
>  ac97 audio codec   
>  ide   
>  compact flash   
>  2 *  100khz to 25Mhz  DSS  frequency genorators    
>  a spartan 3  xc3s400 fpga (75% avalable for user ip)  
>  64MB ddr video ram    
>  dvi-i video (both digital and analog)  
>  composite video output   
>  a 32 dio fpga port / expansion bus ( allowing for 50Mhz + signal  
> clocking )  
>  a lower speed  dio and analog expansion port  
>   
>  on a 160mm * 100mm 4 layer pcb    
>   
>  if verification of the design goes ok then the prototypes should be  
> under construction in the next 3 months , and allowing another 2 to  
> 3 months for the software port and ip core writing before the design  
> is totaly finalised   
>   
> anyone interested in getting involved in the development ether email  
> me at the email on the schematics , or  in irc chat on freenode.net  
> channel #openhardware   
>   
> (sorry that this is slightly off topic)  
>   
> Dave  (achiestdragon)  
>  
> 
>   
>
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> 
> Yahoo! Groups Links
>
>
>
> 
>
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>


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