In wrestling with the SPI interface (on a 7350 but it's really the Cirrus
processor) talking to a Microchip ADC (MCP3202, MCP3204, MCP3208) I have
observed that the Cirrus processor won't generate clock pulses needed by the
ADC device to transmit its data unless there is something in the processor's
transmit buffer. I didn't see this fact documented in the Cirrus documentation
anywhere.
The Microchip devices say they want commands right-justified which is partially
true. The device will work if the data isn't but the trailing bits will cause
SPI clock pulses to be generated but not enough to complete the receiving word
so you end up with a few MSB bits.
In addition, the timing of the device is a little funky in that fully
right-justified data results in the bit 11 of the ADC sample value to be
missed. My hackish solution is to right-justify the command value and shift it
left one bit.
But then things get weird. Even though I can see the ADC sample value being
clocked on a logic analyzer, I don't get the data in the SPI data buffer right
away. I have to wait until the receive buffer is not empty (via the SPI status
register), peek the value (which is 0), wait until the receive buffer is not
empty again and peek the value again.
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