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[ts-7000] Re: SPI interface observation

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Subject: [ts-7000] Re: SPI interface observation
From: "andreas queisser" <>
Date: Mon, 11 Oct 2010 16:58:51 -0000

I'm trying to get SPI kernel support working for the 7300 so your post caught 
my eye.

--- In  "Blair" <> wrote:
>
> In wrestling with the SPI interface (on a 7350 but it's really the Cirrus 
> processor) talking to a Microchip ADC (MCP3202, MCP3204, MCP3208) I have 
> observed that the Cirrus processor won't generate clock pulses needed by the 
> ADC device to transmit its data unless there is something in the processor's 
> transmit buffer.  I didn't see this fact documented in the Cirrus 
> documentation anywhere.
> 

Not sure I understand your comment right but in SPI you always have to clock 
something out to receive something. There isn't a separate write or read, you 
just clock and the data flows in both directions. Unless you're bit-banging the 
interface the master typically has to write dummy data into the TX register, 
then wait for the RX-done interrupt. At that point the transaction is complete.

> The Microchip devices say they want commands right-justified which is 
> partially true.  The device will work if the data isn't but the trailing bits 
> will cause SPI clock pulses to be generated but not enough to complete the 
> receiving word so you end up with a few MSB bits.
> 
> In addition, the timing of the device is a little funky in that fully 
> right-justified data results in the bit 11 of the ADC sample value to be 
> missed.  My hackish solution is to right-justify the command value and shift 
> it left one bit.
> 
Don't know enough about the Microchip devices to comment intelligently, most 
ADCs I've seen have some kind of fixed word size (8 or 16 bit) for transactions 
of any kind.

> But then things get weird.  Even though I can see the ADC sample value being 
> clocked on a logic analyzer, I don't get the data in the SPI data buffer 
> right away.  I have to wait until the receive buffer is not empty (via the 
> SPI status register), peek the value (which is 0), wait until the receive 
> buffer is not empty again and peek the value again.
>
Maybe you're getting the dummy data from when you send out the command and then 
the actual data value? An SPI interface that has the master send a command word 
and then return a value would work that way.

Andrew





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