Impulse C was at the back of my mind when I was talking about running
C code on FPGA.
Obviously you can't use C as a HDL language.
--- In David Hawkins <> wrote:
>
> Hi Chris,
>
> >> That being said, I'm a hardened VHDL coder, and wouldn't consider
> >> this technology anywhere near mature ;)
> >
> > I think that's a safe assumption. I can imagine that they
designed a
> > parser-generator that scans C for specific structures, generating
VHDL
> > or something at a lower level and also obviously doing variable
> > replacements in the rest of the C code. I've often thought about
this
> > myself, but I wouldn't really call it running C code.
>
> Yeah, my impression was they're trying to use C as an HDL
> language, rather than taking C code and 'magically' transforming
> it into an FPGA implementation.
>
> The code snippets I saw expressed parallelism using tasks;
> much like you would with an RTOS.
>
> I haven't had a chance to look through the book, or try writing
> code. Its on my 'things to play with' list.
>
> > Certain things that would be nice to know would be if it respects
> > sharing an fpga with a separate core, if certain pins would be
off
> > limits, and other various constraints.
>
> I'm pretty sure the C-to-HDL process will just give you a component.
> All the rest would be done with the vendor tools.
>
> > Thats definitely an interesting area of software though, in any
case.
> >
> > I wonder if there is a similar open source project?
>
> I haven't heard of one. Altera has their C-to-HDL compiler too,
> though I haven't looked at it.
>
> Too many fun distractions ... so little time :)
>
> One interesting comment from Pellerin was that a driver for this
> technology was financial institutions that are considering
> converting their racks of blade processors into FPGA processor
> to improve power/performance. The main problem with adoption
> of FPGAs is the legions of C-coders familiar with financial
> processing that are currently at a loss as to how to use FPGA
> technologies.
>
> Cheers,
> Dave
>
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