--- In "ian.scanlon" <> wrote:
> Perhaps you missed something in your tests. From the data you
> posted, it is clear that you are receiving your data, it just has one
> extra bit clocked on at the end. The SPI transfer is a short, well
> defined event. How close is the /ss signal to the clock last clock
> edge 1) at low frequency 2) high frequency? What is generating
> the /ss signal? You should really count the number of clock edges
> (pos or neg -what ever you use) that are within the /ss period, with
> a scope. If the signals are generated by an external master, those
> settings should be checked too. To confirm the 'extra clock' theory
> you could use a few values that will give well defined bit patterns.
> If you send 0x0001, I expect you will get 0x0002. 0x0080 -> 0x0100 ...
I've tested the I2S controler of the ep9302 mapped on the SSP pin.This
controler is use to acquire stereo audio signal.
I only use the receiver channel in slave mode. I always use the same
external master at 3MHz with 16 bit lengh data. The I2S need an extra
pin to asserv the righ anf left channel of the audio stream. To catch
data in the I2S fifo, the left and the right channel msut be sent!
In this I2S configuration, all work, and I lose no data !! I only
receive the data by interrupt, I can also use the DMA controler ...
This test help me to think there is a hard synchronous bug in the SSP
receiver in SPI slave mode.
------------------------ Yahoo! Groups Sponsor --------------------~-->
Check out the new improvements in Yahoo! Groups email.
http://us.click.yahoo.com/6pRQfA/fOaOAA/yQLSAA/CFFolB/TM
--------------------------------------------------------------------~->
Yahoo! Groups Links
<*> To visit your group on the web, go to:
http://groups.yahoo.com/group/ts-7000/
<*> To unsubscribe from this group, send an email to:
<*> Your use of Yahoo! Groups is subject to:
http://docs.yahoo.com/info/terms/
|