--- In "suptouch" <> wrote:
>
> --- In "ian.scanlon" <scanlon.design@>
wrote:
> >
> > I had a similar problem (with different uC). If you look at the
bit
> > pattern for all of your data, it is shifted one bit to the left.
I
> > suspect this is a problem with the spi /ss and clock signals ->
edges
> > are close together and as speed goes up, some setup or hold time
is
> > being violated. When I had this problem, it was simply a matter
of
> > changing the SPI mode. The idle clock state was reversed. If you
> > can, check the /ss and clock edges at the end of the transfer
with a
> > scope, then check the timing specs. Also make sure you are using
the
> > correct mode, clocking on the wrong edge will often work at low
> > speeds.
> > Ian
>
> I've tested all the slave mode with the SPO (clock polarity) and SPH
> (clock phase) registers. I never succed ;-(
>
> For the /ss, I also thak abouthold and setup time , but nothing seem
> to be specified in the user manual or datasheet. I've tried with a
1/2
> clock hold time, one clock , and more, but I never succed ;-((
>
> Now, I will try with the I2S controllor (on SSP pin) which seem be
> compatible with the SPI signal without frame signal. I will
configure
> the receiver channel in 16 bit slave mode. Somebody try it ?
>
Perhaps you missed something in your tests. From the data you
posted, it is clear that you are receiving your data, it just has one
extra bit clocked on at the end. The SPI transfer is a short, well
defined event. How close is the /ss signal to the clock last clock
edge 1) at low frequency 2) high frequency? What is generating
the /ss signal? You should really count the number of clock edges
(pos or neg -what ever you use) that are within the /ss period, with
a scope. If the signals are generated by an external master, those
settings should be checked too. To confirm the 'extra clock' theory
you could use a few values that will give well defined bit patterns.
If you send 0x0001, I expect you will get 0x0002. 0x0080 -> 0x0100 ...
Ian
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