--- In "ian.scanlon" <> wrote:
>
> I had a similar problem (with different uC). If you look at the bit
> pattern for all of your data, it is shifted one bit to the left. I
> suspect this is a problem with the spi /ss and clock signals -> edges
> are close together and as speed goes up, some setup or hold time is
> being violated. When I had this problem, it was simply a matter of
> changing the SPI mode. The idle clock state was reversed. If you
> can, check the /ss and clock edges at the end of the transfer with a
> scope, then check the timing specs. Also make sure you are using the
> correct mode, clocking on the wrong edge will often work at low
> speeds.
> Ian
I've tested all the slave mode with the SPO (clock polarity) and SPH
(clock phase) registers. I never succed ;-(
For the /ss, I also thak abouthold and setup time , but nothing seem
to be specified in the user manual or datasheet. I've tried with a 1/2
clock hold time, one clock , and more, but I never succed ;-((
Now, I will try with the I2S controllor (on SSP pin) which seem be
compatible with the SPI signal without frame signal. I will configure
the receiver channel in 16 bit slave mode. Somebody try it ?
Yahoo! Groups Links
<*> To visit your group on the web, go to:
http://groups.yahoo.com/group/ts-7000/
<*> To unsubscribe from this group, send an email to:
<*> Your use of Yahoo! Groups is subject to:
http://docs.yahoo.com/info/terms/
|