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[ts-7000] Re: problem with SSP : spi format + Slave Mode

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Subject: [ts-7000] Re: problem with SSP : spi format + Slave Mode
From: "ian.scanlon" <>
Date: Wed, 05 Jul 2006 21:23:57 -0000
I had a similar problem (with different uC). If you look at the bit 
pattern for all of your data, it is shifted one bit to the left.  I 
suspect this is a problem with the spi /ss and clock signals -> edges 
are close together and as speed goes up, some setup or hold time is 
being violated.  When I had this problem, it was simply a matter of 
changing the SPI mode. The idle clock state was reversed.  If you 
can, check the /ss and clock edges at the end of the transfer with a 
scope, then check the timing specs. Also make sure you are using the 
correct mode, clocking on the wrong edge will often work at low 
speeds.


Ian


--- In  "suptouch" <> wrote:
>
> Dear brian ,
> 
> What's you're configuration, slave or master  ?
> In slave mode do you use the SPI_FRAME ?
> 
> When I look with my oscilliscope nothing seem to be wrong, but the
> received data is ! I'm not sure that Crosstalk is the explanation :
> 
> I've invetigate more and I've observe this :
> 
> The quartz on the TS7300 board is a 14.7456MHz. When I work with
> external master on 14.7456MHz/16 = 921.6KHz all work well. If I'm 
not
>  on this frequence (less or more), I've catching error. Perhaps, 
it's
> not a true SPI slave controller and it work like an uart.
> 
> The error seem to be always the same. For example when I'm at
> 14.7456MHz/4 = 3.68MHz, in 8 bit slave mode, the spi controller seem
> to catch one more bit  at the end ! Example : If I send
> 1,2,3,4,5,6,7,8,9,10,11,12. I always catch 
3,4,7,8,11,12,15,16,19,20,23,24
> 
> I've try to put the SPI in 7 bit slave mode with 8bit data from the
> master, and the catched data is correct (but I've to use the 
SPI_frame) !!
> 
> 
> 
> 
> --- In  Brian Newberry <briannewberry2@> 
wrote:
> >
> > I encountered a similar problem when trying to use the TS-7200 SPI
> port and I don't think its your software or the way you are trying 
to
> set up as the slave.  It may be a problem with your physical setup 
or
> a limitation thereof.  My problem was the interference that the 
signal
> lines caused on one another.  The crosstalk between the wires was
> significant enough to hose the communication completely past a 
certain
> speed.  SPI is a great way to get high speed communication when the
> two chips communicating are on the same board where small traces of
> PCB are used to connect devices, but the bandwidth should be limited
> by trying to connect using a cable especially one of any significant
> length.
> >    
> >   If you have access to an oscilliscope try sending the same byte
> multiple times and try to capture each signal line on the screen.  
If
> you do this I think you will see that when two lines go low or high
> simultaneously this will cause a spike on the other lines large 
enough
> to mess up the transmission.  Obviously this kind of interference 
will
> not allow your reciever to interpret the data correctly.
> >    
> >   It is also very important to make sure your wires are all the 
same
> length.  This will skew your results which gets worse as your clock
> speed increases.
> >    
> >   What I did to get my system to work was used a short length of
> ribbon cable to connect the TS-7200 SPI to my peripheral.  This gave
> me the exact same length on all wires and allowed me to put ground
> lines between every signal.  This is a trick I think is done on IDE
> cables as well to help mitigate crosstalk on the wires.  I was still
> only able to get speeds of up to 1.1 MHz to work flawlessly.  As I
> sped up the clock my performance degraded.  So even with my setup I
> still didn't get much faster than what you are describing that you
> have already acheived.
> >    
> >   So it may be you've done everything right and will still be 
unable
> to get the high speeds that you want.
> >    
> >   Brian
> > 
> > suptouch <suptouch@> wrote:
> >           I've develop a driver module for the SSP in SPI slave 
mode.
> > I 've an interrupt on the SSP fifo to catch the received data.
> > 
> > When I work at 850KHz, all work, all the received data are true 
but
> > when I try with 1.7MHz or faster (I've try with 2.4MHz or 3MHz), 
some
> > data are bad :
> > - in 8 bit mode the first bit is some time bad
> > - in 16 bit mode , some data are lost.
> > 
> > In master mode , the max frequency is 3.645MHz.
> > 
> > What's the max frequency than can use in slave mode ?
> > Is there condition to use it ?
> > 
> > --- In  "suptouch" <suptouch@> wrote:
> > >
> > > Perhaps, I've two ideas :
> > > 
> > > 1/ 
> > > My SPI slave test program is in user space.
> > > Can I use the SPI in user space ? or have I to develop it in 
kernel
> > > space ? why ?
> > > 
> > > 
> > > 2/ 
> > > 
> > > The SPI is also use with the eeprom, and I presume that at the 
boot ,
> > > it's use in master ...
> > > 
> > > Is here a special procedure to configure SPI to slave from 
master ?
> > > 
> > > 
> > > 
> > > --- In  "suptouch" <suptouch@> wrote:
> > > >
> > > > I need to use the SSP (synchronous serial port) of the TS7300 
in 16
> > > > bit SPI slave mode. In the final project, I need to work with 
a fast
> > > > SPI (3MHz or faster), in continous mode. I will implement a 
SPP
> module
> > > > to do it and perhaps use the DMA to fill a RAM buffer.
> > > > 
> > > > The clock is connected to the SPI_CLK so to the SCLK1 of the 
EP9302.
> > > > The out of the master is connected to the SPI_MISO so to the
> SSPRX1 of
> > > > the EP9302.
> > > > 
> > > > For the first test with the SPI, I'm trying with a reduced 
master
> > > > (8bit, 250KHz, not continous mode). The signal is like the 
19.8
> figure
> > > > (page 506) in the user manuel so with the SPO and SPH 
activated.
> > > > 
> > > > After reading the EP9301 user manual, while inspiring to me 
with the
> > > > spp.c driver in the mach-ep93xx and the tempSensor.c, I've 
develop
> > > > this small test program :
> > > > 
> > > > ssp_page = mmap(0, getpagesize(), PROT_READ|PROT_WRITE, 
MAP_SHARED,
> > > > fd, SSP_PAGE);
> > > > 
> > > > /* 1.) Set enable bit(SSE) in register SSPCR1*/
> > > > POKE32( (unsigned long)(ssp_page + SSPCR1), SSPC1_SSE );
> > > > 
> > > > /* 2.) Write other SSP config registers(SSPCR0 & SSPCPSR)*/
> > > > POKE32( (unsigned long)ssp_page + SSPCR0, 
(SSPCR0_FRF_MOTOROLA |
> > > > SSPCR0_SPH | SSPCR0_SPO | SSPCR0_DSS_8BIT) ); 
> > > > 
> > > > /* 3.) Clear the enable bit(SSE) in register SSPCR1*/
> > > > POKE32( (unsigned long)(ssp_page + SSPCR1), 0x00 ); 
> > > > 
> > > > /* 4.) Set the enable bit(SSE) in register SSPCR1*/
> > > > POKE32( (unsigned long)(ssp_page + SSPCR1), (SSPC1_MS |
> SSPC1_SSE) ); 
> > > > 
> > > > /* Done with configuration now lets read ...*/
> > > > while(1)
> > > > {
> > > > val = PEEK32((unsigned long)(ssp_page + SSPSR));
> > > > if(val & SSPSR_RNE)
> > > > {
> > > > //read the data
> > > > val = PEEK32( (unsigned long)(ssp_page + SSP_DATA) );
> > > > printf("The test is:0x%x ", val);
> > > > printf(" ## SSPSR : 0x%x \n",PEEK32((unsigned long)(ssp_page 
+ 
> > > > SSPSR))&0x0F);
> > > > }
> > > > }
> > > > /* end program */
> > > > 
> > > > When I send a data from the master, my program catch 
sometimes a
> good
> > > > character ... but I've to try to send lot of time to catch 
one. When
> > > > I've read the character the RNE flag stay up in the status 
register
> > > > SSPSR and so I continue to catch the same character !
> > > > 
> > > > Perhaps, I've a bad configuration for the slave mode and I 
don't
> read
> > > > correctly in the SSP. I can't find more information in the 
user
> > > manual ...
> > > > 
> > > > I seek for someone witch use the SSP in slave SPI ... but also
> for any
> > > > other proposal 
> > > > 
> > > > Thanks !
> > > >
> > >
> > 
> > 
> > 
> >          
> > 
> >             
> > ---------------------------------
> > Do you Yahoo!?
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> >
>









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