The 32khz is an output from the CPLD to the Controller.
The 32khz input of the controller is suseptable to noise, so the CPLD provides
it with a clean square waveform by dividing the 14.7456MHz clock by 450 to
get 32khz. At the same time it uses this clock for the watchdog timer.
-Curtis.
On March 6, 2006 04:44 am, anand bhavnani wrote:
> hi all,
>
> thks jesse
>
> is it that the 32khz input to the cpld is for the operation of the watchdog
timer?
> can i disable the cpld's watchdog timer?
> can i totally do away with the watchdog timers on my board? in that case
what will be the issues i will face.
>
> yours,
> Anand.
>
>
> Jesse Off <> wrote: The on-CPU watchdog is broken
and unreliable. There is errata on
> the processor silicon itself for this. The processor chip can't be
> relied upon to reset itself at all actually and the Linux kernel has
> been modified to use the external watchdog for software resets.
>
> //Jesse Off
>
>
> --- In anand bhavnani <> wrote:
> >
> > hi all,
> >
> > Curtis Monroe <> wrote:
> > The CPLD does more than just NAND flash management. It also:
> > - handles control signals on the PC104 bus,
> > - has a watchdog timer,
> >
> > the 9302 processor also has a watchdog timer, then why does the
> cpld have another watchdog timer.
> >
> > good bye,
> > Anand.
> >
> >
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