you can turn the watchdog on the cpld off by
writing 0x05 to 0x23C00000, then 0x00 to 0x23800000.
But if you system hangs you don't have the benefit of the watchdog rebooting
it for you.
-Curtis.
#define TS7200_WATCHDOG_CTRL 0x23800000 // read/write
// must feed watchdog less than 30uSecs before writing this reg
// val 0x00 = watchdog disabled
// val 0x01 = 250 mSec watchdog reset counter
// val 0x02 = 500 mSec watchdog reset counter
// val 0x03 = 1000 mSec watchdog reset counter
// val 0x04 = reserved
// val 0x05 = 2000 mSec watchdog reset counter
// val 0x06 = 4000 mSec watchdog reset counter
// val 0x07 = 8000 mSec watchdog reset counter
#define TS7200_WATCHDOG_FEED 0x23C00000 // write only
// val 0x05 = feed the watchdog to restart the reset counter
// bit 2 = pulses at 32kHz (I think)
On March 6, 2006 04:43 am, anand bhavnani wrote:
> hi all,
>
> thks jesse
>
> is it that the 32khz input to the cpld is for the operation of the watchdog
timer?
> can i disable the cpld's watchdog timer?
> can i totally do away with the watchdog timers on my board? in that case
what will be the issues i will face.
>
> yours,
> Anand.
>
>
> Jesse Off <> wrote: The on-CPU watchdog is broken
and unreliable. There is errata on
> the processor silicon itself for this. The processor chip can't be
> relied upon to reset itself at all actually and the Linux kernel has
> been modified to use the external watchdog for software resets.
>
> //Jesse Off
>
>
> --- In anand bhavnani <> wrote:
> >
> > hi all,
> >
> > Curtis Monroe <> wrote:
> > The CPLD does more than just NAND flash management. It also:
> > - handles control signals on the PC104 bus,
> > - has a watchdog timer,
> >
> > the 9302 processor also has a watchdog timer, then why does the
> cpld have another watchdog timer.
> >
> > good bye,
> > Anand.
> >
> >
> > " MINDSET: Its Everything " Anonymous
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