You can adjust the system clock speed by changing the PLL (phased locked loop)
settings for the EP9302. The EP9302 multiplies and divides the 14.7456MHz
input, from the external crystal, to give you the system frequency.
Read about it in the EP9301 or EP9312 User Guides. Its in the SYSCON chapter.
It was also mentioned in this newsgroup in the past. If you do a search you'll
find someone has writen code to slow down the controller to reduce power
consumption during idle time.
The JTAG for the EP9302 is not brought out to external pins in the TS boards.
There is a posting in this news group where a skilled engineer brought out the
JTAG by soldering directly the the EP9302 pins on the controller. (It seems
pretty incredible this guy managed to solder these, seeing as the pins are
only ~0.20mm wide and ~0.30mm apart).
-Curtis.
On March 2, 2006 01:37 am, joel garner wrote:
> The manual mentions that the processor clock is dynamically adjustable
from 0 to 200 MHZ but doesn't mention how... can anyone please help me out...
> i want to get the JTAG CONNECTIONS OUT to a header...so that i
can programme the in-circuitprogrammable CPLD...but i have no clue about how
to do that
> can anyone suggest how can i take them out
>
> chill,
> Joel
>
>
> ---------------------------------
> Yahoo! Mail
> Bring photos to life! New PhotoMail makes sharing a breeze.
Yahoo! Groups Links
<*> To visit your group on the web, go to:
http://groups.yahoo.com/group/ts-7000/
<*> To unsubscribe from this group, send an email to:
<*> Your use of Yahoo! Groups is subject to:
http://docs.yahoo.com/info/terms/
|