On Wed, Mar 01, 2006 at 10:37:25PM -0800, joel garner wrote:
> The manual mentions that the processor clock is dynamically adjustable
> from 0 to 200 MHZ but doesn't mention how... can anyone please help me
> out...
The CPU frequency (in normal operation) is equal to the PLL1 output
divided by the FCLKDIV divisor. By default on the TS7250, PLL1 outputs
something like 400.05 MHz, and the allowable FCLKDIV divisors are either
2, 4, 8 or 16, so you can run the CPU at 200, 100, 50 or 25 MHz.
You _can_ run at other frequencies, but you'd have to reprogram PLL1,
and that can affect a number of peripherals. Check the 'syscon' section
of the EP93xx User's Guide for all the info.
> i want to get the JTAG CONNECTIONS OUT to a header...so
> that i can programme the in-circuitprogrammable CPLD...but i have no
> clue about how to do that
> can anyone suggest how can i take them out
A very fine soldering iron? :-)
cheers,
Lennert
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