Hi all,
I am developing a project using the TS-7300, and am currently trying to test
the FPGA section. I am finding that when using the opencores boilerplate (from
2006), that the board seems to work/ lock up without apparent cause. The same
fpga rbf file compiled by quartus 8.1 web edition on the open cores ts7300_top,
works, (ie cpu keeps running after fpga load). Then sometimes stops working.
(ie cpu stops after fpga load) i presume there is a timing glitch which is
either causing a momentary glitch in the interrupt line (unlikely as I have
tried setting the irq7_pad to hi z at all times (ethernet core is removed).
I read somewhere and can't find ther reference that there is a known glitch
from using combinational logic on the wb bridge, not syychronous logic?
The short question is: is there a reliable working boilerplate out there? Also
sdram core would be nice ;)
regards,
Mike
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