Re: [ts-7000] Re: ts7300 fpga open core test load

I havn't had the problem you're describing.. I did notice some intermittent irqs a while ago, though I think they've gone away :)  I can't offer more insight right now, let me know how it goes, if you could post your code on the board I would like to see what you did.

--- On Mon, 3/30/09, findmike62 <> wrote:

From: findmike62 <>
Subject: [ts-7000] Re: ts7300 fpga open core test load
To:
Received: Monday, March 30, 2009, 2:41 AM

--- In .com, mike.mcdonald0@ ... wrote:
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> Hi,
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> I've encountered this problem, there is nothing wrong with the boilerplate ts7300_top. the lockup is likely because you are holding the interrupt line high and not releasing it.  The interrupt should just be a short active high pulse.
actually it happens when I use the boilerplate WITHOUT any modifications, and also when I modify the code to set the irq to high z at ALL times. I have been making some progress by doing a total re-write but trying to use the boilerplate as a reference for what the input timings are. right now I get a data error about once per 100k cycles, so I am still looking, The error is in the fl_d_pad[7.. 0], my read strobe is not quite timed right. Anyway, with my total re-write, and dma and irqs set as input pins, aand the data bus drivers controlled by bd_oe, the FPGA has yet to hang the cpu. On the other hand I don't have a working register yet sooo.

Mike

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> Also make sure non of the other drivers that expect the FPGA image to be there are running when you load your fpga image, this is documented elsewhere on the board.
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> --Mike
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>
> --- On Sun, 3/29/09, findmike62 <finndmike62@ ...> wrote:
> From: findmike62 <finndmike62@ ...>
> Subject: [ts-7000] ts7300 fpga open core test load
> To: .com
> Received: Sunday, March 29, 2009, 3:11 AM
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> Hi all,
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> I am developing a project using the TS-7300, and am currently trying to test the FPGA section. I am finding that when using the opencores boilerplate (from 2006), that the board seems to work/ lock up without apparent cause. The same fpga rbf file compiled by quartus 8.1 web edition on the open cores ts7300_top, works, (ie cpu keeps running after fpga load). Then sometimes stops working. (ie cpu stops after fpga load) i presume there is a timing glitch which is either causing a momentary glitch in the interrupt line (unlikely as I have tried setting the irq7_pad to hi z at all times (ethernet core is removed).
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> I read somewhere and can't find ther reference that there is a known glitch from using combinational logic on the wb bridge, not syychronous logic?
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> The short question is: is there a reliable working boilerplate out there? Also sdram core would be nice ;)
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> regards,
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> Mike
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