Re: [ts-7000] ts7300 fpga open core test load

Hi,

I've encountered this problem, there is nothing wrong with the boilerplate ts7300_top. the lockup is likely because you are holding the interrupt line high and not releasing it.  The interrupt should just be a short active high pulse.

Also make sure non of the other drivers that expect the FPGA image to be there are running when you load your fpga image, this is documented elsewhere on the board.

--Mike


--- On Sun, 3/29/09, findmike62 <> wrote:

From: findmike62 <>
Subject: [ts-7000] ts7300 fpga open core test load
To:
Received: Sunday, March 29, 2009, 3:11 AM

Hi all,

I am developing a project using the TS-7300, and am currently trying to test the FPGA section. I am finding that when using the opencores boilerplate (from 2006), that the board seems to work/ lock up without apparent cause. The same fpga rbf file compiled by quartus 8.1 web edition on the open cores ts7300_top, works, (ie cpu keeps running after fpga load). Then sometimes stops working. (ie cpu stops after fpga load) i presume there is a timing glitch which is either causing a momentary glitch in the interrupt line (unlikely as I have tried setting the irq7_pad to hi z at all times (ethernet core is removed).

I read somewhere and can't find ther reference that there is a known glitch from using combinational logic on the wb bridge, not syychronous logic?

The short question is: is there a reliable working boilerplate out there? Also sdram core would be nice ;)

regards,

Mike

__._,_.___

Your email settings: Individual Email|Traditional
Change settings via the Web (Yahoo! ID required)
Change settings via email: =Email Delivery: Digest | m("yahoogroups.com?subject","ts-7000-fullfeatured");=Change Delivery Format: Fully Featured">Switch to Fully Featured
Visit Your Group | Yahoo! Groups Terms of Use | =Unsubscribe

__,_._,___