--- In David Hawkins <> wrote:
>
> Hi,
>
> > Thanks for all the answers!
>
> No problem. Its good to discuss projects with others, if only
> to be forced to look at your own ideas from another angle.
>
> > It looks like Altera's OpenCore license only allows generating .sof
> > programming files. Here is a snippet from p3 of
> > (http://www.altera.com/literature/an/an320.pdf):
> > "If all the megafunctions in your design that are not fully licensed
> > support OpenCore Plus hardware evaluation, the Quartus II
> > software allows you to generate a special programming file, an
> > SRAM Object File (<top-level project>_time_limited.sof), that
> > you can use to program a device with the Quartus II
> > Programmer and an Altera download cable. However, you
> > cannot use it to program memory. No .vqm, or atom-level .vo, or
> > .vho files are generated."
>
> Yeah, that looks like it'll be a pain. However, if you were
> developing on NIOS II for a product, then you'd have to get
> a license eventually. If that was the case, you could get it
> now. Or, if you are with a university, you can get the
> licenses for free, you just have to join the university
> program. They'll also donate you a DE2 board if you ask.
>
> > Also, looking at TS-7300's documentation again, they only mention CPLD
> > programming via JTAG, which means NIOS II with OpenCore licence is not
> > an option for this board. Unless I am mistaken?
>
> I'm pretty sure the FPGA can be programmed from a header,
> its just that the pinout of the header is not Altera's
> JTAG pinout.
It looks from the schematics that JTAG is indeed connected to Cyclone
2. They probably did not mention this info due to a much nicer way of
uploading bitstreams via EP9302. Last night I've made an adapter for
my jtag and will test it out soon.
>
> > Nios was one of the original options due to several reasons:
> > - For another project that I will be mainly using TS-7300 for, I would
> > need to use FPGA for I/O peripheral development.
>
> Right, but with the EP9302 as your processor running uCOS-II,
> you can just use the Opencores Verilog project for the
> custom I/O and you do not need the tethered license for
> the NIOS II core, i.e., split your project objectives
> RTOS on the ARM core, and custom I/O in the FPGA.
>
> > - Since I have experience with uBlaze, I think adding NIOS would be
> > fairly easy
> > - NIOS II has a well documented port of uC/OS II, which is supposed to
> > save time
>
> The book on uCOS-II documents all you need to know.
>
> > My other option is using a microcontroller like Motorola HSC12, which
> > would be way simpler than FPGA since it would involve only software.
> > However, I would have to do two things at the same time (work with
> > Cyclone 2 for one project and HSC12 for another in parallel). Also, I
> > own TS-7300 and not Motorola board yet.
> >
> > Now, you brought up an interesting option. A port of uC/OS to EP9302.
> > I've never done this before. Sounds complex, yet not too bad. From
> > your report:
> > "A μCOS-II port requires the definition of the data types on the
> > processor, assembly language routines for critical section protection,
> > interrupt handling, and context switching, and the
> > definition of C coded hook functions."
> > I would have to consider a few things before deciding because I have a
> > lot of time constraints at the moment.
>
> Yeah, but the EP9302 is an ARM processor, so most of the work is
> done - since the report is for an LPC2000 ARM processor. The
> main difference will be in the processor setup and interrupt
> controller. If you look at TS's notes, I recall you can boot your
> own custom code from an SD-card using their initial bootloader.
> So you can use that, and you do not have to worry about initialization
> of the board, as their code does that. The only thing you have to do is
> read the EP9302 manual and determine whether it uses a different
> interrupt controller than the LPC2000.
>
> The power-on sequence would be; TS bootloader runs, initializes the
> board, copies the boot code off the SD-card, and jumps into it.
> Your uCOS-II port would then start at main(), initialize a timer,
> and then start the OS. You'd create tasks just as you would on
> any other uCOS-II system. Your custom I/O would be an ARM memory
> address, as per the TS Linux examples.
It would be a great thing to learn one of the days! I don't think I
can allow myself to consider it now though. Here I need a proven
system to build on for my application, just as I am managing time
between work, classes, research and other things. But nevertheless
I'll note this info for the future!
>
> >> Why did you get a TS-7300 for this project?
> > TS-7300 is available from another project. It just happens that it's
> > available and I can combine two different things on one platform/FPGA.
>
> Ok, fair enough.
>
> > I also have Xilinx Virtex II and Spartan 3 boards. I've seen uC/OS II
> > ports to uBlaze, but have to check whether there is a risk of spending
> > too much time porting it to newest version of uBlaze (if the existing
> > ports are for older versions). Again, the time is quite crucial here.
> >
> > I'll look into porting to EP9302 and prices for HSC12 devboards.
>
> I'd start by looking back at the TS-7300 documents.
>
> I'm certain I read somewhere that they provides puts() output
> code from their initial bootloader. I'd write something like
> a hello-world program that sends a message to the serial port,
> and then after that figure out how to program an interrupt.
Could you please elaborate on the puts() function usage in the "hello
world (write to serial)" program for understanding how interrupt
handlers are programmed. Are you suggesting using puts() inside the
hello world? and set breakpoints to see where the program jumps during
the puts command?
> Once you have an interrupt working, everything else is
> pretty easy. For example, here's a uCOS-II port I did to a
> DSP with a completely different processor core etc.
>
> http://www.ovro.caltech.edu/~dwh/correlator/pdf/dsp_programming.pdf
>
> The key thing to note is that the porting sequence is identical.
Thanks,
Victor
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