--- In David Hawkins <> wrote:
>
> Hi,
>
> > Has anyone tried putting NIOS II on Cyclone 2, TS-7300 board?
>
> I haven't tried it, but it should be possible.
>
> > My main interest here is whether I would be able to play with NIOS II
> > embedded system using a free license for several months and what are
> > the restrictions. From Altera's website, it looks like SOPC comes with
> > a free web license. However, it is not clear whether NIOS II can be
> > used for free and for how long. I've read about the JTAG connection to
> > the board (required for the free version), but again need
> > clarification here.
>
> I'm pretty sure the free version only works while the
> Altera JTAG cable is connected, and it might be time
> limited in addition to that. The TS7300 does not have
> a standard Altera JTAG cable connector, but I believe
> all the JTAG signals are on a connector, so you'll
> have to build an adapter.
>
> So first thing you'll want to try is building the adapter
> to get the Cyclone device detected by Quartus.
>
> If the NIOS licensing becomes a pain, there is the
> open-source Leon SPARC processor too. Look around the
> Altera site, and you'll find application notes where people
> have implemented the Leon processor. Opencores also has
> some processor designs.
>
> Cheers,
> Dave
>
David,
Thanks for your reply.
Digging more on Altera's website, I found the following information.
Assuming I only use Nios II MegaCore, I am allowed to:
- Generate SRAM Object File (.sof) and program it to the device via
Quartus II Web Edition and Altera download cable
- In thethered mode with a cable, the use is unlimited
- In non-tethered mode, the design will stop functioning after some
time (they say 1 hour or more).
- After the time-out, the device can be re-programmed to continue
evaluation
- To control time limitation, in tethered mode Quartus Programmer
sends signals to the embedded time limiting logic on FPGA resetting
the time.
Reference: http://www.altera.com/literature/an/an320.pdf
I wonder if I can use non-Altera cable to program the device and
evaluate 1 hour at a time in non-tethered mode. This way I can avoid
buying the specific cable and using a simple JTAG programmer. I
haven't tried Altera flow yet, but I think generating .SOF file does
not require the cable. I hope downloading it to FPGA can be also be
done with a generic JTAG. What do you think?
LEON
There are many positive things about Leon3 including a large user
community, asic- and fpga- proven design, etc. It also supports eCos
with drivers for OpenCore 10/100 Mbit Ethernet, which is very attractive.
Is the design flow fairly easy to ramp up on with some
tutorials/experience reports? I will be doing a project that mostly
should concentrate on RTOS development and not on hardware debugging.
Nios II looks very attractive due to the tools it is provided with. I
assume it should be similar to MicroBlaze flow which will speed things
up for me. It would be nice to go open source with Leon, but if it
will take a significantly larger amount of time, I should probably
better leave it for future and just get the Altera's download cable
for this project. Any comments?
Thanks!
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