Hi,
> Digging more on Altera's website, I found the following information.
> Assuming I only use Nios II MegaCore, I am allowed to:
> - Generate SRAM Object File (.sof) and program it to the device via
> Quartus II Web Edition and Altera download cable
> - In thethered mode with a cable, the use is unlimited
> - In non-tethered mode, the design will stop functioning after some
> time (they say 1 hour or more).
> - After the time-out, the device can be re-programmed to continue
> evaluation
> - To control time limitation, in tethered mode Quartus Programmer
> sends signals to the embedded time limiting logic on FPGA resetting
> the time.
> Reference: http://www.altera.com/literature/an/an320.pdf
>
> I wonder if I can use non-Altera cable to program the device and
> evaluate 1 hour at a time in non-tethered mode. This way I can avoid
> buying the specific cable and using a simple JTAG programmer.
If you have a parallel port on your development machine,
you can make up their parallel port adapter very easily,
and just use that.
You can get a USB download cable from Terasic for $50
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=53
eBay sometimes has cheap USB cables too.
> I haven't tried Altera flow yet, but I think generating .SOF file does
> not require the cable. I hope downloading it to FPGA can be also be
> done with a generic JTAG. What do you think?
You can generate the .SOF programming file used by JTAG, or
generate the raw binary file (.RBF) that I think the TS tool
uses. That way you can use TS Linux to reconfigure the FPGA,
and you can just live with the time limit, eg. reset and
reload the configuration every hour :)
> LEON
> There are many positive things about Leon3 including a large user
> community, asic- and fpga- proven design, etc. It also supports eCos
> with drivers for OpenCore 10/100 Mbit Ethernet, which is very attractive.
>
> Is the design flow fairly easy to ramp up on with some
> tutorials/experience reports?
I haven't played with it much. I just noticed the Altera application
examples and downloaded a copy. I have seen software development
activity on a number of groups, so it is popular.
> I will be doing a project that mostly
> should concentrate on RTOS development and not on hardware debugging.
So why bother with the NIOS processor at all? You have an ARM
processor sitting there just begging for a UCOS port, eg. here's
the one I did for the ARM LPCs:
http://www.ovro.caltech.edu/~dwh/ucos/
http://www.ovro.caltech.edu/~dwh/ucos/project_AR1803.pdf
http://www.ovro.caltech.edu/~dwh/ucos/gcc_and_ucosii.zip
The EP9302 would be similar. You could even use the serial
bootloader interface to boot UCOS on the board without
having to overwrite the Flash or SD-card.
> Nios II looks very attractive due to the tools it is provided with. I
> assume it should be similar to MicroBlaze flow which will speed things
> up for me. It would be nice to go open source with Leon, but if it
> will take a significantly larger amount of time, I should probably
> better leave it for future and just get the Altera's download cable
> for this project. Any comments?
I guess my first comment would be what is the end goal for the project?
Why did you get a TS-7300 for this project?
For example, if you're familiar with the Microblaze flow, why not
use a board with a Xilinx FPGA? The Avnet Spartan-3A kit is $50
and comes with download software for bitfiles, but perhaps doesn't
have the resources you require.
Cheers,
Dave
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