Hi Eugen,
> If i will receive an answer from you for my previous post i will be
> very thankful.
Weird, I don't recall seeing that email, though I do have
this one, and the one you just sent.
I also see from the last few emails that came in that you've
got the pointer to the open-cores design.
> Anyway i just looked upon your projects (correlator and
> carma_board) and i see that indeed you are a great engineer.
You're far too kind.
> If it is possible may i ask you for some electrical
> schematics? beacause i like studying PCB's and designs
> and your projects are really impressive.
Sure, you're most welcome to download the project files on
the web (there are OrCAD schematics, and Allegro PCB files,
along with a free Allegro viewer).
Feel free to ask me for comments on board designs or FPGA
designs. I'll try to help/comment if I can.
> I finally purchased a 7300 board as you advice me. I will go for
> implementing my first AND gate in this FPGA .Let's hope this won't be
> a big problem. But there is an aspect I cannot understand. FPGA is
> told to be mapped between physical address 72A0.0000 to 72FF.FFFC ;
> from a simple calculus we can see that addressing of that address
> space cannot be done unless we use at least 22 distinct address
> lines. However as I saw from the schematics that number is much
> smaller. Can you please lighten me up a little by telling me which
> address lines must be used. For example if I want to build a block of
> registers into the FPGA how will I be able to map them. I'm not so
> clear which address lines to use . There are some ISA_ADD and also
> ADD lines. The lines that come directly from the CPU (9302) are the
> ADD lines but their number is small. I don't understand to well how
> the mapping is done.
I haven't used the board for a while. I work in VHDL, and the
opencores project was in Verilog. I'd planned to compile the
open-cores code in Modelsim, and then figure out the VHDL
equivalent. However, playing with the TS-7300 was a side
project that I never got time to work on.
So for your first project on the board you'll need to;
1. Work out what you need to disable under Linux to stop
any Linux-side programs from wanting to access the
devices implemented in the FPGA. Eg. video, serial, etc.
There were posts from a user a while back ... I think her
name was Elizabeth ... I believe she listed what she
disabled to keep Linux happy when the FPGA configuration
was reset/changed.
2. Build your project.
Eg. perhaps turn one LED (or I/O) on, and another off.
The sequence will be;
a) Start a quartus project and select the Cyclone device
used on the board (make sure to select the right
package and speed grade).
You can open up the open-cores design and see what
is used there.
b) Set unused pins to tri-state
*This is important*
If you have a simple design that does not use all the
pins on the FPGA, then by default those unused pins
will drive ground - this will cause a problem with
pins that are supposed to be inputs on the TS-7300
(due to driver conflicts, i.e., an external driver
driving high, while the FPGA tried to drive low).
To override the default setting you need to go to
* Assignments menu -> Device
* Click on the device and pin options button
* Click on the unused pins tab
* Set the pull-down to 'As input tri-stated'
c) create the HDL code for your design, eg. in VHDL
I'm just typing this in, so it might need editing :)
entity ts7300
port (
led : out std_logic_vector(1 downto 0)
)
end entity;
architecture top of ts7300 is
begin
led <= "10";
end architecture;
If you get stuck, let me know, and I'll pull out my board and
play with it. I'm not in my office this week, so won't be able
to help hardware-wise over the next few days, but I can offer
encouragement :)
Regarding the addressing scheme used between the ARM CPU and
the FPGA. I also recall finding that it was confusing! However,
I can't recall the details. I'd have to look back at the schematic
and the open-cores design. I believe there was some multiplexing
of address and data signals performed with the help of the CPLD
on the board. But after that my memory gets hazy.
After you've had a look at the open-cores design, if you still
find the addressing scheme confusing, let me know, and I'll
look at it again and see if I can make sense of it. The
open-cores design did not come with a testbench (eg. a fake ARM
bus cycle generator) so that makes the code a little
user-unfriendly. However, it is open-source, so if you plan
on working in Verilog, you could take a shot at designing a
testbench to generate ARM CPU cycles to write and read from
the registers in the open-cores design.
Cheers,
Dave
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