Thank you mike for the information.
Please tell me if the ts7300_top.v is from TS repository or from open
cores ,I'm a bit to tired now to find it.
Thank you
Eugen
--- In .com, mike.mcdonald0@ ... wrote:
>
> This is something I have been working on, hopefully I can give a
> partial answer and someone really knowledgeable can fill gaps/
correct
> mistakes. Most of this I found out by looking at ts7300_top.v
>
>
>
> There are 24 bits of address to the FPGA coming from various
places, I
> can't comment on how exactly this works, but I don't think it's
> important to what you're doing.
>
>
>
> The code uses a wishbone bridge to combine 2 16 bit read/writes in
to
> one 32 bit read/write. So as far as I can tell, data must be
written
> to the FPGA in blocks of 32 bits (4 bytes), in other words, the
data
> word size is 32-bits in the FPGA address space.
>
>
>
> bits [23:2] of the address are used to index each 32-bit data word
i.e.:
>
>
>
> 0x72A00000 = 1110010101000000000 000000000000
>
>
>
> is 0x28000 = 1010000000000000000 000
>
>
>
> 0x72A00004 = 1110010101000000000 000000000100
>
>
>
> is 0x280001 = 1010000000000000000 001
>
>
>
> 0x72A00008 = 1110010101000000000 000000001000
>
>
>
>
>
> is 0x280002 = 1010000000000000000 010
>
>
>
> etc...
>
>
>
>
>
> --- On Tue, 1/6/09, pointdexter67 <pointdexter67@ ...> wrote:
> From: pointdexter67 <pointdexter67@ ...>
> Subject: [ts-7000] Re: TS-7300 fpga code
> To: .com
> Received: Tuesday, January 6, 2009, 12:01 AM
>
>
>
>
>
>
>
>
>
>
>
>
>
> Hello Dave ,
>
> I finally purchased a 7300 board as you advice me. I will go for
>
> implementing my first AND gate in this FPGA .Let's hope this won't
be
>
> a big problem. But there is an aspect I cannot understand. FPGA is
>
> told to be mapped between physical address 72A0.0000 to 72FF.FFFC ;
>
> from a simple calculus we can see that addressing of that address
>
> space cannot be done unless we use at least 22 distinct address
>
> lines. However as I saw from the schematics that number is much
>
> smaller. Can you please lighten me up a little by telling me which
>
> address lines must be used. For example if I want to build a block
of
>
> registers into the FPGA how will I be able to map them. I'm not so
>
> clear which address lines to use . There are some ISA_ADD and also
>
> ADD lines. The lines that come directly from the CPU (9302) are the
>
> ADD lines but their number is small. I don't understand to well how
>
> the mapping is done.
>
> Thank you very much.
>
> Eugen
>
>
>
> Hello Dave ,
>
>
>
> I fina
>
>
>
> --- In .com, David Hawkins <dwh@> wrote:
>
> >
>
> > Hi Eugen,
>
> >
>
> > > Can you please tell me which is the machanism of writing new
code
>
> in
>
> > > the FPGA (I'm talking about the Lattice XP2 from the 7390
TPC ).
>
> As
>
> > > far as i know this chip contains the code for VGA , SD and a
>
> couple
>
> > > of serial ports.
>
> > >
>
> > > 1. Can i copy the actual contents of the chip for future
>
> restauration?
>
> > >
>
> > > 2. If i make a new code , for using the new functionality i
think
>
> i
>
> > > have to write a device driver that will communicate with the
new
>
> > > function of the Lattice.??
>
> > >
>
> > > 3. Please explan me a bit how this interaction between linux
and
>
> > > Lattice is done from your point of view.
>
> > >
>
> > > My intention is to take an example from opencores and use it
for
>
> > > learning.
>
> >
>
> > I haven't used/looked at the 7390 ... so I'll take a look on
>
> > EmbeddedArm and give you general comments.
>
> >
>
> > The FPGA is a Lattice XP2, so you'd write your HDL code using
>
> > Lattice's tool (ispLevel).
>
> >
>
> > From the FPGA datasheet:
>
> >
>
> > http://www.lattices emi.com/document s/HB1004. pdf
>
> >
>
> > LatticeXP2 devices combine a Look-up Table (LUT) based FPGA
>
> > fabric with non-volatile Flash cells in an architecture
>
> > referred to as flexiFLASH.
>
> >
>
> > So the FPGA is an SRAM-based FPGA that configures at power-on
>
> > from an on-chip/in-package Flash. Altera's MAX II devices
>
> > are similar.
>
> >
>
> > Since the Flash is on-chip, its likely the device has a
>
> > security feature where you can not copy the current image,
>
> > so you would need to get that directly from TS if you
>
> > wanted to recover your FPGA.
>
> >
>
> > The data sheet comments about 'dual-boot technologies' ,
indicating
>
> > two images could be in the on-chip Flash, so you might be able
>
> > to exploit that feature if the FPGA has been wired to support it.
>
> >
>
> > However, without direct customization help from TS, there is a
high
>
> > probability that you would *brick* the TS-7390. I would not
>
> > recommend you heading this route.
>
> >
>
> > The OpenCores example is for the TS-7300 and its Altera Cyclone
>
> > FPGA. Though the TS-7390 design is similar, and the TS internal
>
> > HDL code for the FPGAs is probably almost identical, it will be
>
> > a lot harder for you to customize the TS-7390.
>
> >
>
> > Why not stick with using the TS-7300?
>
> >
>
> > Cheers,
>
> > Dave
>
> >
>