Hello Dave ,
I finally purchased a 7300 board as you advice me. I will go for
implementing my first AND gate in this FPGA .Let's hope this won't be
a big problem. But there is an aspect I cannot understand. FPGA is
told to be mapped between physical address 72A0.0000 to 72FF.FFFC ;
from a simple calculus we can see that addressing of that address
space cannot be done unless we use at least 22 distinct address
lines. However as I saw from the schematics that number is much
smaller. Can you please lighten me up a little by telling me which
address lines must be used. For example if I want to build a block of
registers into the FPGA how will I be able to map them. I'm not so
clear which address lines to use . There are some ISA_ADD and also
ADD lines. The lines that come directly from the CPU (9302) are the
ADD lines but their number is small. I don't understand to well how
the mapping is done.
Thank you very much.
Eugen
Hello Dave ,
I fina
--- In .com, David Hawkins <> wrote:
>
> Hi Eugen,
>
> > Can you please tell me which is the machanism of writing new code
in
> > the FPGA (I'm talking about the Lattice XP2 from the 7390 TPC ).
As
> > far as i know this chip contains the code for VGA , SD and a
couple
> > of serial ports.
> >
> > 1. Can i copy the actual contents of the chip for future
restauration?
> >
> > 2. If i make a new code , for using the new functionality i think
i
> > have to write a device driver that will communicate with the new
> > function of the Lattice.??
> >
> > 3. Please explan me a bit how this interaction between linux and
> > Lattice is done from your point of view.
> >
> > My intention is to take an example from opencores and use it for
> > learning.
>
> I haven't used/looked at the 7390 ... so I'll take a look on
> EmbeddedArm and give you general comments.
>
> The FPGA is a Lattice XP2, so you'd write your HDL code using
> Lattice's tool (ispLevel).
>
> From the FPGA datasheet:
>
> http://www.lattices emi.com/document s/HB1004. pdf
>
> LatticeXP2 devices combine a Look-up Table (LUT) based FPGA
> fabric with non-volatile Flash cells in an architecture
> referred to as flexiFLASH.
>
> So the FPGA is an SRAM-based FPGA that configures at power-on
> from an on-chip/in-package Flash. Altera's MAX II devices
> are similar.
>
> Since the Flash is on-chip, its likely the device has a
> security feature where you can not copy the current image,
> so you would need to get that directly from TS if you
> wanted to recover your FPGA.
>
> The data sheet comments about 'dual-boot technologies' , indicating
> two images could be in the on-chip Flash, so you might be able
> to exploit that feature if the FPGA has been wired to support it.
>
> However, without direct customization help from TS, there is a high
> probability that you would *brick* the TS-7390. I would not
> recommend you heading this route.
>
> The OpenCores example is for the TS-7300 and its Altera Cyclone
> FPGA. Though the TS-7390 design is similar, and the TS internal
> HDL code for the FPGAs is probably almost identical, it will be
> a lot harder for you to customize the TS-7390.
>
> Why not stick with using the TS-7300?
>
> Cheers,
> Dave
>