--- In Eddie Dawydiuk <> wrote:
>
> Hello,
>
> >> If TS have found that a specific assembly instruction
> >> is required, then you may want to rename their PEEK
> >> and POKE as fpga_in_le16(), fpga_out_le16(), or 'be' if
> >> the processor is running in big-endian mode (I forget).
> >> At least then the code will look more standard than
> >> with PEEK and POKE scattered through-out.
>
> The issue you are running into is that older ARM cores only had
> strb/ldrb and str/ldr instructions. There was no strh/ldrh, as a result
> gcc will emit two 8 bit reads/writes unless instructed otherwise. This
> is why we provided the PEEK/POKE routines to abstract this away. If one
> chooses to not use the PEEK/POKE routines they should pass gcc the
> -mcpu=arm9 to ensure the strh/ldrh instructions are used. Below is an
> example demonstrating the issue.
>
> e.g.
>
> :joff]#cat test.c
> #include <stdio.h>
>
> int main(void) {
> volatile char *foo = (char *)0x12345678;
> volatile short *foos = (short *)0x12345678;
> volatile int *fool = (int *)0x12345978;
>
> *foo = 0xaa;
> *foos = 0xaaaa;
> *fool = 0xaaaaaaaa;
> }
> :joff]#gcc test.c -S -o test.s
> :joff]#gcc test.c -S -o test_arm9.s -mcpu=arm9
> :joff]#diff -u test.s test_arm9.s
> --- test.s Thu Sep 13 10:10:28 2007
> +++ test_arm9.s Thu Sep 13 10:10:44 2007
> @@ -20,11 +20,10 @@
> mvn r3, #85
> strb r3, [r2, #0]
> ldr r2, [fp, #-20]
> - mov r3, #170
> - strb r3, [r2, #0]
> - strb r3, [r2, #1]
> - ldr r2, [fp, #-24]
> ldr r3, .L2+8
> + strh r3, [r2, #0] @ movhi
> + ldr r2, [fp, #-24]
> + ldr r3, .L2+12
> str r3, [r2, #0]
> mov r0, r3
> ldmea fp, {fp, sp, pc}
>
HAH!
Thanks, Eddie. That reflects exactly what I was seeing. Now at least
I know what to do and how to go about cleaning it up.
:-)
--Yan
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