[ts-7000] PC104 Read Timing Specs

To:
Subject:	[ts-7000] PC104 Read Timing Specs
From:	"ndivner" <>
Date:	Thu, 08 Feb 2007 00:27:50 -0000

Hi All,

I am designing a PC104 interface module using a Xilinx Xpla3 CPLD 
chip and I would like to know when exactly does the ts-7260 sample 
the data on a read. I am wondering what Setup and Hold is required 
relative to the trailing edge of IOR_N when presenting the data to 
the bus? The only data I have is an old Intel PC Isa bus spec.

Many thanks in advance,

Noel Diviney.



 
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