[ts-7000] Re: PC104 Read Timing Specs

["Jesse Off" <>]

--- In  "ndivner" <> wrote:
>
> Hi All,
> 
> I am designing a PC104 interface module using a Xilinx Xpla3 CPLD 
> chip and I would like to know when exactly does the ts-7260 sample 
> the data on a read. I am wondering what Setup and Hold is required 
> relative to the trailing edge of IOR_N when presenting the data to 
> the bus? The only data I have is an old Intel PC Isa bus spec.
> 
> Many thanks in advance,

It samples on the rising edge of IOR#/MEMR#.  Actually -- its a little 
bit before as there is a propagation delay from the CPU to the CPLD to 
the IOR#/IOW# signal.  Make sure you have about 10ns of valid data 
setup time before IOR# deasserts.

//Jesse Off



 
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