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Re: [ts-7000] Re: TS-7400 and GPIO register

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Subject: Re: [ts-7000] Re: TS-7400 and GPIO register
From: "Breton M. Saunders" <>
Date: Tue, 23 Jan 2007 22:58:17 +0000
Hi Jesse,

  Thanks for the details.
  I've chosen to stick with 8 bit writes for the CPLD registers.
  I was using the eeprom as a test for a developing a better SPI driver. 
  I've got it running at > 2MHz now without DMA.  I'll likely go to a DMA driver when I need even faster performance.

  Thanks,

    -Brett

Jesse Off wrote:

--- In .com, "Breton M. Saunders"
<breton.saunders@...> wrote:
>
> Quick question r/e CPLD register addresses on the ts-7400:
>
> Are they all byte only registers? For example, if I do a
> readl(0x12c00000) will I get the contents of all four addresses
(0x12c0
> 0000, ..1, ..2, ..3) or must I readb on each one?

Those registers at 0x12c00000 will work this way. The CPU will break
up the 32 bit access to 4 8bit reads and the bus cycle will take 4
times as long. The only difference between reading the regs this way
and using 4 individual byte loads is that the read strobe will be
asserted for the entire (4x longer) bus cycle. Those registers have
a 100% combinational data path from the address lines to the data bus
so they're ok. The UART registers don't work that way however, so
you can't just do a single 16-bit read and expect to get both
registers in one cycle for those. Most all other CPLD registers will
behave as you expect for >8bit reads though.

>
> Same question applies for writes.
>
> I know that the EEPROM chip select register (0x2300_0000) only
works if
> I perform byte wide reads/writes on it.

Be careful with writes. The way the 0x2300_0000 address is decoded,
it is aliased. i.e. 0x2300_0001, 0x2300_0002, and 0x2300_0003 are
all the same register. When you write the 32-bit value 0x12345678,
the CPU will break down the 32-bit cycle into 4 8-bit cycles and
execute them LSB first. The last write will be 0x12 to address
0x2300_0003 and will be what you end up writing to the register.

Your safest course of action is to only use 8-bit reads on CPLD
registers. (strb, ldrb arm insns)

//Jesse Off


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