I've been using the opencore code for some time, and getting random
sudden linux reboots after data transfers, but with the fix committed
on Dec. 13 I now seem to be able to transfer large amounts of data
without this happening.
This has meant I've been able to write a little test program, which
just writes a word to the FPGA, then reads it back (to/from dummyreg).
The values written are just the index i, modulo 997. When I do this, I
get something like 1 or 2 errors every million words, where the value
read back is apparently always either 0 or 192 instead of the expected
value just written. e.g.:
Incorrect: 4827 192 should be 839
Incorrect: 421369 0 should be 635
(first number is the index of the word in the test, next number is the
actual value read back from FPGA, last number is the expected number
(the one written to FPGA))
The bitstream is just compiled directly from a CVS checkout, I can
provide the C code I'm using, it just uses /dev/mem and mmap, then
reads/writes the first user location.
Before the Dec.13 fix, I had taken the code and removed the ethernet
and extra I/O to make a module that could easily be used separately,
for example in a VHDL project, etc. I will commit the changes to this
and check it still works, would this code and/or the C test program be
useful to anyone? I would appreciate it if the code could be checked
by someone at TS just to make sure I haven't broken the wishbone bridge :)
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