--- In "fpga_test_dev" <>
wrote:
>
> I've been using the opencore code for some time, and getting random
> sudden linux reboots after data transfers, but with the fix
committed
> on Dec. 13 I now seem to be able to transfer large amounts of data
> without this happening.
>
> This has meant I've been able to write a little test program, which
> just writes a word to the FPGA, then reads it back (to/from
dummyreg).
> The values written are just the index i, modulo 997. When I do
this, I
> get something like 1 or 2 errors every million words, where the
value
> read back is apparently always either 0 or 192 instead of the
expected
> value just written. e.g.:
>
> Incorrect: 4827 192 should be 839
> Incorrect: 421369 0 should be 635
>
> (first number is the index of the word in the test, next number is
the
> actual value read back from FPGA, last number is the expected number
> (the one written to FPGA))
I actually just found another bug in the bridge since the Dec 13th
fix. Unfortunately, it was very difficult to reproduce, very random,
and seemed to be specific to each bitstream generated. 99% of the
time in my experience these types of heisenbugs have been because of
asynchronous logic or unexpected metastability. I don't use asynch
logic often, but in this one case (wishbone bridge) I used it with 4
flip-flops to make the bridge as fast as possible. Since ruling out
metastability, I looked a little closer at the 4 flip-flops I was
using asynch sets/clrs on and found the problem as a potential glitch
on one of the flip-flop's asynch set signals.
Lesson learned. Problem solved. Fix should be committed to
opencores.org shortly.
//Jesse Off
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