Ok, once again answering my own question, it seems like things didn't
change. I had forgotten that the vid registers didn't have enough
bits to accomodate a 600 vertical blit, so it has to be done in two
passes.
--- In "gamehoser" <> wrote:
>
> Actually, looking at things, it seems more likely that the registers
> have changed layout a bit and my bit packing doesn't do the right
> thing anymore. Were there any changes other than assigning bit 12 to
> the mask flag? In particular, the height field did not have enough
> bits to do a full 600 blit, so I'm betting some other stuff had to be
> changed up as well.
>
> James
>
> --- In "gamehoser" <james.singer1@> wrote:
> >
> > Ok. That makes total sense about you having limited timing options.
> > I only pointed out the 56Hz in case it wasn't intentional. :).
> >
> > It does seem like the page offsets to the blit instruction have
> > changed though. For a rectangle operation I used to use drawpage<<19
> > as the offset to that page, but it now seems like that's somehow not
> > correct since all of my blits seem to be happening earlier in memory
> > than I would expect. Any tidbits of info that'd help me fix this? I
> > figure Peter probably has documentation or just flat out knowledge of
> > the layout since he requested it, but I thought I'd ask here first.
> >
> > James
> >
> > --- In "Jesse Off" <joff@> wrote:
> > >
> > > --- In "gamehoser" <james.singer1@> wrote:
> > > >
> > > > Alright, I just fired this up to give it a shot. It sync'd up
just
> > > > fine on my monitor, but I did notice that the monitor is reporting
> > > > 56Hz for the refresh rate. If it's supposed to be hitting 60
> for your
> > > > 10.4" display, then that could be your issue with it only
> getting 790
> > > > pixels. If the pixel clock was not at the right rate, I could see
> > > > this happening.
> > >
> > > Its supposed to be hitting 56Hz. I don't have a lot of options for
> > > easily attainable pixel clock rates with the PLL circuitry I
have on
> > > the FPGA. I ran 640x480 at a 25Mhz pixel clock and am currently
> > > running 800x600 at 37.5Mhz. The SVGA timing spec calls for
38.1Mhz--
> > > but a delta of 600Khz is well within the margins of most CRT sync
> > > circuitry. A low 56Hz vert refresh may cause eye fatigue on old
CRT
> > > monitors, but should be a non-issue for LCD's and also conserves
> SDRAM
> > > bandwidth and power though admittedly rendering 800x600 at 60Hz
only
> > > takes 54 of the ~130 megabytes/sec of SDRAM to FPGA bandwidth I
have.
> > >
> > > The vertical off-center on the original was more an artifact of my
> > > horizontal timing state machine than of the refresh rate. Its a
> bit of
> > > a black art to get a timing that syncs up centered with most
monitors
> > > and LCDs without actually talking to the monitor. I'm a bit
> surprised
> > > that the first didn't sync up well on LCDs as it sync'ed
perfectly on
> > > my 10 yr old test CRT and was very close to the original SVGA 56Hz
> > > timing. All I changed in the 2nd bitstream was the ratio
between the
> > > horizontal front/back porch and shortened the length of the
> horizontal
> > > sync pulse.
> > >
> > > //Jesse Off
> > >
> >
>
Yahoo! Groups Links
<*> To visit your group on the web, go to:
http://groups.yahoo.com/group/ts-7000/
<*> Your email settings:
Individual Email | Traditional
<*> To change settings online go to:
http://groups.yahoo.com/group/ts-7000/join
(Yahoo! ID required)
<*> To change settings via email:
<*> To unsubscribe from this group, send an email to:
<*> Your use of Yahoo! Groups is subject to:
http://docs.yahoo.com/info/terms/
|