--- In Jason Stahls <> wrote:
>
> On 7/21/2011 1:35 PM, Jon L wrote:
> > Oh i'd be very interested in this. my email is if you could
> > forward your project.
> >
> > I'm confused based on what you wrote though, you got a 75khz signal, but
> > was that from the ts7500 or from an fpga subsystem? I guess I'm gonna
> > search this forum...
>
> He did it in the FPGA, search back a few months I remember reading it.
> The TS7500 code simply tells the FPGA what to do.
>
> --
> Jason Stahls
>
I just looked it up. I see!!! this looks like just what I want. to surmise
what I think I see:
1) there is an FPGA on the ts7500 where you can write some code.
2) to make room for it some of the existing code in the ts7500 fpga was removed
(CAN??? what is that?) and additional poke features were added to allow a
DO signal to run at 1/1000 the 75mhz clock speed, at a user selectable duty
cycle through a seperate poke.
this is an area of the ts7500 programming I haven't explored. NOW I have ISE
9.2, 10.1, and I see a bit of verilog code in the file ts7500.rar in the
files section, is this the code to regenerate the ???? for the 7s7500???
I'm very excited about this.
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