Re: [ts-7000] ts-7500: how fast can I get a digital ouput to pulse?

[Razvan-Ionut Stoian <>]

It's very slow. In order to make it fast and immune to the absence of real time preemption in your kernel, you should do everything at FPGA level.

All of the above apply to the majority of SBCs that have no support for RT and high resolution timers.  

1. it's slow -> it depends on how fast you can send commands to the FPGA over the bus.
2. RT preemption -> no such thing for that processor. In other words, it will be impossible to maintain a 50% duty cycle.
3. modify the Verilog source code for you FPGA, so the  GPIOs can be switched at a rate dictated by an external stable clock signal coupled to one of the FPGA inputs.

One more thing. I tried to do the same using a different processor, and the best I could get in terms of timing (RT and high resolution timers enabled) was 10 us with a jitter of  200 us for a realtime task with a period of 1 ms. So, no matter what you want to do, if you want fast and precise timings, you have to learn about FPGAs (steep learning curve, but it's worth it :-))

just my $.02
 

--- On Tue, 7/19/11, Jon L <> wrote:

From: Jon L <>
Subject: [ts-7000] ts-7500: how fast can I get a digital ouput to pulse?
To:
Date: Tuesday, July 19, 2011, 2:07 PM

 

say I want to pulse a digital output pin to pulse with a ts-7500 with a 50% duty cycle.

what is the fastest signal I can get and what is the best way to program such a signal?

I can only think of this in C:

do {
sbuslock();
setdiopin(pin, 0);
usleep(1);
setdiopin(pin,1);
sbusunlock();
}
while ( hell_not_frozen_over);

but is this reliable?

and what will this do to the other processes running on the system?

is this a cpu hog or is there a better way to do this?

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