Hi!
Months ago I posted a code I was creating for my master thesis. I needed a
75000 khz signal with different duty cycle. I did it with the ts7500. Why don't
you search for it?
I think it's a good approach for what you need. It's done at the FPGA level,
and well, it's in Spanish, but if you email me I can help you.
Search for PWM with ts7500! There are some files at the forum too!
Regards
Enrique
--- In "Jon L" <> wrote:
>
>
>
> Yes thanks for info. In the past I've done this with a drigmorn Fpga as a
> subsystem:
>
>
> http://enterpoint.co.uk/products/spartan-3-development-boards/drigmorn-1/
>
> where I set up an rs232 comm link to command the drigmorn from a controller
> device (in this case it will be the ts-7500)
>
> but I was hoping that there was a solution on board with the ts-7500
>
> I was also wondering if it was worth trying to use an arduino board:
>
> http://www.adafruit.com/products/50
>
> the hand waivers all say "oh why don't you just usa an arduino..." of course
> I have to do the implemenation...
>
>
>
> --- In Razvan-Ionut Stoian <razvan_ionut_stoian@>
> wrote:
> >
> > It's very slow. In order to make it fast and immune to the absence of real
> > time preemption in your kernel, you should do everything at FPGA level.
> >
> > All of the above apply to the majority of SBCs that have no support for RT
> > and high resolution timers. Â
> >
> > 1. it's slow -> it depends on how fast you can send commands to the FPGA
> > over the bus.
> > 2. RT preemption -> no such thing for that processor. In other words, it
> > will be impossible to maintain a 50% duty cycle.
> > 3. modify the Verilog source code for you FPGA, so the GPIOs can be
> > switched at a rate dictated by an external stable clock signal coupled to
> > one of the FPGA inputs.
> >
> > One more thing. I tried to do the same using a different processor, and the
> > best I could get in terms of timing (RT and high resolution timers enabled)
> > was 10 us with a jitter of 200 us for a realtime task with a period of 1
> > ms. So, no matter what you want to do, if you want fast and precise
> > timings, you have to learn about FPGAs (steep learning curve, but it's
> > worth it :-))
> >
> > just my $.02
> > Â
> >
> > --- On Tue, 7/19/11, Jon L <jleslie48@> wrote:
> >
> > From: Jon L <jleslie48@>
> > Subject: [ts-7000] ts-7500: how fast can I get a digital ouput to pulse?
> > To:
> > Date: Tuesday, July 19, 2011, 2:07 PM
> >
> >
> >
> >
> >
> >
> >
> > Â
> >
> >
> >
> >
> >
> >
> >
> >
> >
> > say I want to pulse a digital output pin to pulse with a ts-7500 with
> > a 50% duty cycle.
> >
> >
> >
> > what is the fastest signal I can get and what is the best way to program
> > such a signal?
> >
> >
> >
> > I can only think of this in C:
> >
> >
> >
> > do {
> >
> > sbuslock();
> >
> > setdiopin(pin, 0);
> >
> > usleep(1);
> >
> > setdiopin(pin,1);
> >
> > sbusunlock();
> >
> > }
> >
> > while ( hell_not_frozen_over);
> >
> >
> >
> > but is this reliable?
> >
> >
> >
> > and what will this do to the other processes running on the system?
> >
> >
> >
> > is this a cpu hog or is there a better way to do this?
> >
>
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