>> If the 5V logic is TTL, then it will be. If its some
>> ancient CMOS family (HC I think), then it might not
>> be TTL compatible, and in that case you will want to
>> use an open-collector (or tri-state) and a pull-up
>> to 5V. For the tri-state, your 3.3V logic level goes
>>
>
> Thanks! (x2!) I'm not currently dealing with ancient
> CMOS, but should that happen, what would be a reasonable
> value for the resistor?
Its a trade-off of the RC time versus the input current
to the devices you've got the pull-up attached to.
If your R is too big, then the IR drop across it can
pull the voltage on the line lower than Vih(min) of
the receiver.
But if your R is too small, then when you try to drive
the line low, you have to sink 5V/I into your drivers.
The Tinylogic parts have lots of drive, so can go
to small Rs, eg. 1K.
I tend to use 10K or 1K depending on what reference design
I'm copying :) However, in the design you're looking at
the PCI_LOCAL_RST# output driver must be pretty weak
as when I had a 1k pull-up the low voltage was 200mV,
(3.3V - 200mV)/1000 = 3.1mA. So changing that to 10k
would have fixed the issue, but I found the reset IC
had a 25k internal pull-up so I changed the pull-up to
no-mount.
> And in the ESD sort-of-friendly circuit you described,
> you put 100 ohm in series on both input an output?
100-Ohms would likely be too high for the output. But
for an initial guess, its as good as any other value.
Generally if you're buffering a clock, you want the
source termination (output resistor plus output driver
impedance) to match the transmission line impedance.
So if your PCBs were controlled impedance at 65-Ohms,
you'd want to tweak things. For a 2-layer barebones
board, just use 100-ohms on the input and output.
> I'm studying your schematic, and see a 10K pull up resistor,
> but not resistors in series on the NC7SZ125s.
In this case, I'm not expecting fingers zapping those
inputs. Look on the JTAG connector pages, eg. p43 and p44,
and you'll see examples of Rs between headers and buffers,
and then Rs used as dual-source terminations to send
copies to multiple destinations, see p77 for another
example. The TinyLogic buffers have pretty good drive
so you can use them as clock distribution buffers.
If you have lots of clock loads, then rather than
routing the clocks from a single buffer, you route
a tree; a few clocks from the source, and then split
as needed to make the layout nice. In some cases use
the dual buffer to get 2 or 4 clocks, in other cases
use the single clock buffer to get 1 or 2 clocks.
Use the tri-state control if power-sequencing is needed.
Eg. p97. I've hedged my bets and run the signal into
a buffer and around a buffer, so I can investigate
jitter issues.
Resistor pads are effectively free, use them :)
> It's the little things ;)
Yep, its always nicer to hear why something was done,
rather than to look at a schematic and scratch your head.
Cheers,
Dave
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