I have just zipped up a Lattice ispLever 7.2 project allowing customers to
generate custom TS7500 FPGA projects.
ftp://ftp.embeddedARM.com/misc/ts7500_opencore.zip
Once downloaded, open up the project in ispLever (free download from Lattice)
and double-click "Generate Data File (JEDEC)"
A few minutes later, a ts7500_opencore.jed will be produced that can be copied
over to the SBC and loaded into the FPGA SRAM via the command "ts7500ctl
--loadfpga ts7500_opencore.jed". FPGA reloading takes approx 2.8 seconds.
Some notable points about the FPGA opencore:
*) The opencore FPGA bitstream has all functionality of the default bitstream
including SD, XUARTs, SPI NOR flash, watchdog, etc..
*) SD and XUART cores are Lattice .ngo (binary netlists), but Verilog sources
to everything else is included.
*) You need the newest ts7500ctl just released that has the "--loadfpga"
option at ftp://ftp.embeddedARM.com/ts-arm-sbc/ts-7500-linux/binaries/ts-utils/
*) You also need jed2vme executable in your path (same FTP location as above)
to use ts7500ctl --loadfpga on a .jec file.
*) jed2vme can be used to turn the 1.2Mbyte JEDEC .jed file into a 190Kbyte
.vme file. This .vme file can also be gzip'ed or bzip2'ed into (~90Kbyte)
.vme.bz2 or .vme.gz and "ts7500ctl --loadfpga" will decompress automatically.
*) Licensing will be BSD (not GPL) to allow for proprietary closed-source
modifications. However, there will be a caveat that you can only use the
sources on our own TS hardware. Basically, as long as you do it on our boards,
you can do whatever you want with it.
*) The intention is to make the default initrd "linuxrc" attempt to
automatically load a bitstream at "/ts7500.vme.gz" if it exists since it is
best to reload the FPGA as early as possible before userspace driver daemons
are all started.
Also, I've released the source code to all the userspace *ctl utilities we
wrote at ftp://ftp.embeddedARM.com/ts-arm-sbc/ts-7500-linux/sources/ .
//Jesse Off
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