Re: [ts-7000] Phil's ADC kernel module thank you

[mike ingle <>]

Thanks, I will try the timing constraints as you have suggested.  The design is registered, and de-meta'd to the extreme.  All the other parts (board to board serial protocols accross several clock domains ...) work flawlessly,  just the cpu to fpga interface is occasionally off.  Unfortunately the raw ep9302 bus is not presented, but rater one with varying delays for the lower 8 bits, and with the cpu control signals converted in the black box cpld.

 

 

Personally I think there is a market for a product with the following characteristics:

 

1.  Provides a resonably fast CPU with a good linux port.  FPGA connected, and project provided which bridges the CPU bus to something like wishbone, with timing constraints in the the project already.  Candidates Marvell 88F6281 or TI omap 3530.

 

2.  The development environment in a VM.  Providing the kernel source, and patches, and config.  Open Embedded config.  QT version >= 4.5 cross compiled and ready to use in VM. 

 

Just my 2 cents.  

 

Mike

 

 

On Thu, Sep 3, 2009 at 10:20 AM, David Hawkins <> wrote:

 

> I find that the design is subject to routing, and
> that there should be timing constraints on the cpu / cpld to fpga bus,
> which I don't know. I messed with it and am down to an occasional (1 in
> a billion) write error to register space (0x72a00000). Always the lsb.

A good rule for FPGA design is to register buses as they
come onto the FPGA, and register them as they leave, and
then constrain the design so that the I/O element registers
are used. Then put a reasonable tsu/th constraint so that
the input delays internal to the FPGA are programmed
correctly (I forget if the Cyclone has these), and then
add an unreasonable clock-to-output delay and P&R the
design. Then relax that constraint until its met.

I've pasted in an example below for the bus in a Stratix II
design.

Try something like this. These constraints can be entered
in the Tcl console, or you can use the assignments editor
pull-down menus and select them.

Cheers,
Dave

# Input/output A/D bus
set_instance_assignment\
-name TSU_REQUIREMENT "1.0 ns"\
-from clk_fpga_fb_in -to fpga_ad
set_instance_assignment\
-name TH_REQUIREMENT "1.0 ns"\
-from clk_fpga_fb_in -to fpga_ad
set_instance_assignment\
-name TCO_REQUIREMENT "6.0 ns"\
-from clk_fpga_fb_in -to fpga_ad

# Output controls
set_instance_assignment\
-name TCO_REQUIREMENT "6.0 ns"\
-from clk_fpga_fb_in -to fpga_ads
set_instance_assignment\
-name TCO_REQUIREMENT "6.0 ns"\
-from clk_fpga_fb_in -to fpga_read
set_instance_assignment\
-name TCO_REQUIREMENT "6.0 ns"\
-from clk_fpga_fb_in -to fpga_last
set_instance_assignment\
-name TCO_REQUIREMENT "6.0 ns"\
-from clk_fpga_fb_in -to fpga_wrvalid_rdready

# Input control
set_instance_assignment\
-name TSU_REQUIREMENT "1.0 ns"\
-from clk_fpga_fb_in -to fpga_wrready_rdvalid
set_instance_assignment\
-name TH_REQUIREMENT "1.0 ns"\
-from clk_fpga_fb_in -to fpga_wrready_rdvalid

# Fast I/O Registers
set_instance_assignment\
-name FAST_INPUT_REGISTER ON -to fpga_ad
set_instance_assignment\
-name FAST_OUTPUT_REGISTER ON -to fpga_ad
set_instance_assignment\
-name FAST_OUTPUT_REGISTER ON -to fpga_ads
set_instance_assignment\
-name FAST_OUTPUT_REGISTER ON -to fpga_read
set_instance_assignment\
-name FAST_OUTPUT_REGISTER ON -to fpga_last
set_instance_assignment\
-name FAST_OUTPUT_REGISTER ON -to fpga_wrvalid_rdready
set_instance_assignment\
-name FAST_INPUT_REGISTER ON -to fpga_wrready_rdvalid

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