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Re: [ts-7000] Re: ts-7250 settle time (MAX197)

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Subject: Re: [ts-7000] Re: ts-7250 settle time (MAX197)
From: Jim Jackson <>
Date: Sat, 30 May 2009 22:38:06 +0100 (BST)


On Sat, 30 May 2009, charliem_1216 wrote:

>> I'm interested in seeing how fast this can sample, your test sets the 
>> bar at 8k/s with a heavy compilation running. Was that an attempt to 
>> find the maximum or just a test of what you needed?
>
> It was just what I needed.  Here:
> http://tech.groups.yahoo.com/group/ts-7000/message/2085
> Phil reported easily taking data at 22 kS/sec, with 3% CPU.  Note the 
> difference between his example2 and example3 programs: it makes a 
> difference what you do with the data.

I've always been suspicious of cpu usage figures when the load is in the 
kernel - dunno exactly why, but I get a twinge in me joints (might be 
artheritis :-) 3% CPU for 22kS/sec, and issues in the driver at 44sS/sec!

As the sampling is done in a timer ISR, I've always been a bit uneasy about 
jitter on the samples. I'm no ARM processor expert, but from experience 
with other processors just because an interrupt is raised doesn't always 
mean the processor with immediately jump to the ISR. The processor could be 
already be processing an ISR with interrupts disabled, and the interrupt 
will be actioned when interrupts are enabled at the end of the ISR. This 
means that time interval between samples could be subject to some jitter, 
which is likely to get worse the higher the sampling rate.

I was going to see if I could do something to measure the jitter, but I 
never had time and I didn't really need very accurate high sample rates, so 
never persued it. I'd be interested to know if anyone has looked at this.

> Also, the examples won't work until the frequency IOCTL that I broke is 
> fixed.
>>
>> Any idea what IO scheduler would be best to achieve fastest sampling?
>
> I don't think that would have an effect.

ditto.

Jim


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